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    Subject[PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests
    Date
    From: Russell King <rmk+kernel@armlinux.org.uk>

    Re-arrange the tests for which sets of registers are being accessed so that
    it is easier to add further regions later. No functional change.

    Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
    [pali: Fix reading old value in pci_bridge_emul_conf_write]
    Signed-off-by: Pali Rohár <pali@kernel.org>
    ---
    drivers/pci/pci-bridge-emul.c | 61 ++++++++++++++++++-----------------
    1 file changed, 31 insertions(+), 30 deletions(-)

    diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
    index 033bbeb99176..56b2cb741498 100644
    --- a/drivers/pci/pci-bridge-emul.c
    +++ b/drivers/pci/pci-bridge-emul.c
    @@ -418,25 +418,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
    __le32 *cfgspace;
    const struct pci_bridge_reg_behavior *behavior;

    - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
    - *value = 0;
    - return PCIBIOS_SUCCESSFUL;
    - }
    -
    - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
    + if (reg < PCI_BRIDGE_CONF_END) {
    + /* Emulated PCI space */
    + read_op = bridge->ops->read_base;
    + cfgspace = (__le32 *) &bridge->conf;
    + behavior = bridge->pci_regs_behavior;
    + } else if (!bridge->has_pcie) {
    + /* PCIe space is not implemented, and no PCI capabilities */
    *value = 0;
    return PCIBIOS_SUCCESSFUL;
    - }
    -
    - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
    + } else if (reg < PCI_CAP_PCIE_END) {
    + /* Our emulated PCIe capability */
    reg -= PCI_CAP_PCIE_START;
    read_op = bridge->ops->read_pcie;
    cfgspace = (__le32 *) &bridge->pcie_conf;
    behavior = bridge->pcie_cap_regs_behavior;
    } else {
    - read_op = bridge->ops->read_base;
    - cfgspace = (__le32 *) &bridge->conf;
    - behavior = bridge->pci_regs_behavior;
    + /* Beyond our PCIe space */
    + *value = 0;
    + return PCIBIOS_SUCCESSFUL;
    }

    if (read_op)
    @@ -480,11 +480,27 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
    __le32 *cfgspace;
    const struct pci_bridge_reg_behavior *behavior;

    - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
    - return PCIBIOS_SUCCESSFUL;
    + ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
    + if (ret != PCIBIOS_SUCCESSFUL)
    + return ret;

    - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
    + if (reg < PCI_BRIDGE_CONF_END) {
    + /* Emulated PCI space */
    + write_op = bridge->ops->write_base;
    + cfgspace = (__le32 *) &bridge->conf;
    + behavior = bridge->pci_regs_behavior;
    + } else if (!bridge->has_pcie) {
    + /* PCIe space is not implemented, and no PCI capabilities */
    return PCIBIOS_SUCCESSFUL;
    + } else if (reg < PCI_CAP_PCIE_END) {
    + /* Our emulated PCIe capability */
    + reg -= PCI_CAP_PCIE_START;
    + write_op = bridge->ops->write_pcie;
    + cfgspace = (__le32 *) &bridge->pcie_conf;
    + behavior = bridge->pcie_cap_regs_behavior;
    + } else {
    + return PCIBIOS_SUCCESSFUL;
    + }

    shift = (where & 0x3) * 8;

    @@ -497,21 +513,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
    else
    return PCIBIOS_BAD_REGISTER_NUMBER;

    - ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
    - if (ret != PCIBIOS_SUCCESSFUL)
    - return ret;
    -
    - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
    - reg -= PCI_CAP_PCIE_START;
    - write_op = bridge->ops->write_pcie;
    - cfgspace = (__le32 *) &bridge->pcie_conf;
    - behavior = bridge->pcie_cap_regs_behavior;
    - } else {
    - write_op = bridge->ops->write_base;
    - cfgspace = (__le32 *) &bridge->conf;
    - behavior = bridge->pci_regs_behavior;
    - }
    -
    /* Keep all bits, except the RW bits */
    new = old & (~mask | ~behavior[reg / 4].rw);

    --
    2.20.1
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