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    Subject[PATCH v5 15/21] kvm: x86: Add XCR0 support for Intel AMX
    Date
    From: Jing Liu <jing2.liu@intel.com>

    Two XCR0 bits are defined for AMX to support XSAVE mechanism. Bit 17
    is for tilecfg and bit 18 is for tiledata.

    The value of XCR0[17:18] is always either 00b or 11b. Also, SDM
    recommends that only 64-bit operating systems enable Intel AMX by
    setting XCR0[18:17]. 32-bit host kernel never sets the tile bits in
    vcpu->arch.guest_supported_xcr0.

    Signed-off-by: Jing Liu <jing2.liu@intel.com>
    Signed-off-by: Kevin Tian <kevin.tian@intel.com>
    Signed-off-by: Yang Zhong <yang.zhong@intel.com>
    ---
    arch/x86/kvm/x86.c | 7 ++++++-
    1 file changed, 6 insertions(+), 1 deletion(-)

    diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
    index 434986928552..553e4af12edc 100644
    --- a/arch/x86/kvm/x86.c
    +++ b/arch/x86/kvm/x86.c
    @@ -211,7 +211,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs;
    #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
    | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
    | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
    - | XFEATURE_MASK_PKRU)
    + | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)

    u64 __read_mostly host_efer;
    EXPORT_SYMBOL_GPL(host_efer);
    @@ -1010,6 +1010,11 @@ static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
    if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
    return 1;
    }
    +
    + if ((xcr0 & XFEATURE_MASK_XTILE) &&
    + ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
    + return 1;
    +
    vcpu->arch.xcr0 = xcr0;

    if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
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      Last update: 2022-01-05 13:37    [W:4.228 / U:0.120 seconds]
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