Messages in this thread | | | Date | Tue, 4 Jan 2022 15:57:41 +0000 | From | Lorenzo Pieralisi <> | Subject | Re: [PATCH v2 4/5] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET |
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On Fri, Nov 26, 2021 at 02:01:18PM +0530, Kishon Vijay Abraham I wrote: > AM654 RootComplex has a hard coded 64 bit BAR of size 1MB and also has > both MSI and MSI-X capability in it's config space. If PCIEPORTBUS is > enabled, it tries to configure MSI-X and msix_mask_all() adds about 10 > Second boot up delay when it tries to write to undefined location. > > Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET so that > msix_map_region() returns NULL for Root Complex and avoid un-desirable > writes to MSI-X table.
I don't think this is the right fix (it is not even a fix, just a plaster to workaround an issue).
What do you mean by "writing to an undefined location" ?
What does "a hard coded BAR" mean ?
What happens if we _rightly_ write into it (ie to size it) ?
Lorenzo
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/controller/dwc/pci-keystone.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c > index 52d20fe17ee9..73e6626a0d8f 100644 > --- a/drivers/pci/controller/dwc/pci-keystone.c > +++ b/drivers/pci/controller/dwc/pci-keystone.c > @@ -557,8 +557,14 @@ static void ks_pcie_quirk(struct pci_dev *dev) > { 0, }, > }; > > - if (pci_is_root_bus(bus)) > + if (pci_is_root_bus(bus)) { > bridge = dev; > + if (pci_match_id(am6_pci_devids, bridge)) { > + struct resource *r = &dev->resource[0]; > + > + r->flags |= IORESOURCE_UNSET; > + } > + } > > /* look for the host bridge */ > while (!pci_is_root_bus(bus)) { > -- > 2.17.1 >
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