Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Mon, 31 Jan 2022 16:30:40 +0100 | Subject | Re: [PATCH v3] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions |
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On Wed, Jan 26, 2022 at 10:10 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module > clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also > add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 > ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00, > Nov.2021). > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Hi All, > > This patch is from series [0]. Just re-sending this patch as > rest are queued. > > v2->v3: > * Added DRP core clocks > * Included RB and ACK
Thanks for the update! Will queue in a branch shared by DT and clock driver.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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