Messages in this thread | | | From | Tobias Waldekranz <> | Subject | Re: [PATCH net-next 1/2] net: dsa: mv88e6xxx: Improve performance of busy bit polling | Date | Thu, 27 Jan 2022 13:58:12 +0100 |
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On Thu, Jan 27, 2022 at 00:45, Andrew Lunn <andrew@lunn.ch> wrote: > There are a few bit-banging systems out there. For those, i wonder if > 50ms is too short? With the old code, they had 16 chances, no matter > how slow they were. With the new code, if they take 50ms for one > transaction, they don't get a second chance. > > But if they have taken 50ms, around 37ms has been spent with the > preamble, start, op, phy address, and register address. I assume at > that point the switch actually looks at the register, and given your > timings, it really should be ready, so a second loop is probably not > required? > > O.K, so this seems safe.
I think you raise a good point though. Say that you then have this series of events:
1. Bang out ST 2. Bang out OP 3. Bang out PHYADR 4. Bang out REGADR 5. Clock out TA 6. schedule() 7. A SCHED_FIFO/P99 task runs 8. Clock in DATA
- Steps 1 through 5 could plausibly be completed before the bit clears if you are running over some memory mapped GPIO lines - Step 7 could execute for more than 50ms - After step 8, you would see the busy bit set, but your time is up
All of this is of course _very_ unlikely, but not impossible. Should we ensure that you always get at least two bites at the apple?
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