Messages in this thread | | | Date | Wed, 26 Jan 2022 13:10:03 +0200 | From | Mika Westerberg <> | Subject | Re: [PATCH 2/2] PCI/DPC: Disable DPC when link is in L2/L3 ready, L2 and L3 state |
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Hi,
On Wed, Jan 26, 2022 at 03:18:52PM +0800, Kai-Heng Feng wrote: > Since TLP and DLLP transmission is disabled for a Link in L2/L3 Ready, > L2 and L3, and DPC depends on AER, so also disable DPC here.
Here too I think it is good to mention that the DPC "service" never implemented the PM hooks in the first place
> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
One minor comment below, but other than that looks good,
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> --- > drivers/pci/pcie/dpc.c | 61 +++++++++++++++++++++++++++++++----------- > 1 file changed, 45 insertions(+), 16 deletions(-) > > diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c > index 3e9afee02e8d1..9585c10b7c577 100644 > --- a/drivers/pci/pcie/dpc.c > +++ b/drivers/pci/pcie/dpc.c > @@ -343,13 +343,34 @@ void pci_dpc_init(struct pci_dev *pdev) > } > } > > +static void dpc_enable(struct pcie_device *dev) > +{ > + struct pci_dev *pdev = dev->port; > + u16 ctl; > + > + pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); > +
Drop the empty line here.
> + ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; > + pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); > +} > + > +static void dpc_disable(struct pcie_device *dev) > +{ > + struct pci_dev *pdev = dev->port; > + u16 ctl; > + > + pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); > + ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN); > + pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); > +}
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