Messages in this thread | | | Date | Mon, 24 Jan 2022 17:30:04 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH] x86/perf: Default freeze_on_smi on for Comet Lake and later. |
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On Mon, Jan 24, 2022 at 11:00:56AM -0500, Liang, Kan wrote: > > > On 1/24/2022 7:21 AM, Peter Zijlstra wrote: > > On Fri, Jan 21, 2022 at 11:26:44PM -0800, Kyle Huey wrote: > > > Beginning in Comet Lake, Intel extended the concept of privilege rings to > > > SMM.[0] A side effect of this is that events caused by execution of code > > > in SMM are now visible to performance counters with IA32_PERFEVTSELx.USR > > > set. > > > > > > rr[1] depends on exact counts of performance events for the user space > > > tracee, so this change in behavior is fatal for us. It is, however, easily > > > corrected by setting IA32_DEBUGCTL.FREEZE_WHILE_SMM to 1 (visible in sysfs > > > as /sys/devices/cpu/freeze_on_smi). While we can and will tell our users to > > > set freeze_on_smi manually when appropriate, because observing events in > > > SMM is rarely useful to anyone, we propose to change the default value of > > > this switch. > > + Andi > > From we heard many times from sophisticated customers, they really hate > blind spots. They want to see everything. That's why we set freeze_on_smi to > 0 as default. I think the patch breaks the principle.
Well, USR really, as in *REALLY* should not be counting SMM. That's just plain broken.
There's maybe an argument to include it in OS, but USR is ring-3.
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