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    Subject[PATCH 5.16 0212/1039] thermal/drivers/imx8mm: Enable ADC when enabling monitor
    Date
    From: Paul Gerber <Paul.Gerber@tq-group.com>

    [ Upstream commit 3de89d8842a2b5d3dd22ebf97dd561ae0a330948 ]

    The i.MX 8MP has a ADC_PD bit in the TMU_TER register that controls the
    operating mode of the ADC:
    * 0 means normal operating mode
    * 1 means power down mode

    When enabling/disabling the TMU, the ADC operating mode must be set
    accordingly.

    i.MX 8M Mini & Nano are lacking this bit.

    Signed-off-by: Paul Gerber <Paul.Gerber@tq-group.com>
    Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
    Fixes: 2b8f1f0337c5 ("thermal: imx8mm: Add i.MX8MP support")
    Link: https://lore.kernel.org/r/20211122114225.196280-1-alexander.stein@ew.tq-group.com
    Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/thermal/imx8mm_thermal.c | 3 +++
    1 file changed, 3 insertions(+)

    diff --git a/drivers/thermal/imx8mm_thermal.c b/drivers/thermal/imx8mm_thermal.c
    index 7442e013738f8..af666bd9e8d4d 100644
    --- a/drivers/thermal/imx8mm_thermal.c
    +++ b/drivers/thermal/imx8mm_thermal.c
    @@ -21,6 +21,7 @@
    #define TPS 0x4
    #define TRITSR 0x20 /* TMU immediate temp */

    +#define TER_ADC_PD BIT(30)
    #define TER_EN BIT(31)
    #define TRITSR_TEMP0_VAL_MASK 0xff
    #define TRITSR_TEMP1_VAL_MASK 0xff0000
    @@ -113,6 +114,8 @@ static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)

    val = readl_relaxed(tmu->base + TER);
    val = enable ? (val | TER_EN) : (val & ~TER_EN);
    + if (tmu->socdata->version == TMU_VER2)
    + val = enable ? (val & ~TER_ADC_PD) : (val | TER_ADC_PD);
    writel_relaxed(val, tmu->base + TER);
    }

    --
    2.34.1


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