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    Subject[PATCH 5.10 521/563] net: axienet: Wait for PhyRstCmplt after core reset
    Date
    From: Robert Hancock <robert.hancock@calian.com>

    commit b400c2f4f4c53c86594dd57098970d97d488bfde upstream.

    When resetting the device, wait for the PhyRstCmplt bit to be set
    in the interrupt status register before continuing initialization, to
    ensure that the core is actually ready. When using an external PHY, this
    also ensures we do not start trying to access the PHY while it is still
    in reset. The PHY reset is initiated by the core reset which is
    triggered just above, but remains asserted for 5ms after the core is
    reset according to the documentation.

    The MgtRdy bit could also be waited for, but unfortunately when using
    7-series devices, the bit does not appear to work as documented (it
    seems to behave as some sort of link state indication and not just an
    indication the transceiver is ready) so it can't really be relied on for
    this purpose.

    Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
    Signed-off-by: Robert Hancock <robert.hancock@calian.com>
    Reviewed-by: Andrew Lunn <andrew@lunn.ch>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 ++++++++++
    1 file changed, 10 insertions(+)

    --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
    +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
    @@ -516,6 +516,16 @@ static int __axienet_device_reset(struct
    return ret;
    }

    + /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */
    + ret = read_poll_timeout(axienet_ior, value,
    + value & XAE_INT_PHYRSTCMPLT_MASK,
    + DELAY_OF_ONE_MILLISEC, 50000, false, lp,
    + XAE_IS_OFFSET);
    + if (ret) {
    + dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__);
    + return ret;
    + }
    +
    return 0;
    }


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