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    Subject[PATCH 5.15 188/846] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
    Date
    From: Nishanth Menon <nm@ti.com>

    [ Upstream commit d0c826106f3fc11ff97285102b576b65576654ae ]

    A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of
    64 bytes and 16-way set-associative cache structure.

    1MB of L2 / 64 (line length) = 16384 ways
    16384 ways / 16 = 1024 sets

    Fix the l2 cache-sets.

    [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
    [2] https://www.ti.com/lit/pdf/spruiu1

    Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
    Reported-by: Peng Fan <peng.fan@nxp.com>
    Signed-off-by: Nishanth Menon <nm@ti.com>
    Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
    Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
    Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
    index b7005b8031495..df86c36c21134 100644
    --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
    @@ -84,7 +84,7 @@
    cache-level = <2>;
    cache-size = <0x100000>;
    cache-line-size = <64>;
    - cache-sets = <2048>;
    + cache-sets = <1024>;
    next-level-cache = <&msmc_l3>;
    };

    --
    2.34.1


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