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    Subject[PATCH 5.16 0867/1039] drm/amdgpu: Use correct VIEWPORT_DIMENSION for DCN2
    Date
    From: Harry Wentland <harry.wentland@amd.com>

    commit dc5d4aff2e99c312df8abbe1ee9a731d2913bc1b upstream.

    For some reason this file isn't using the appropriate register
    headers for DCN headers, which means that on DCN2 we're getting
    the VIEWPORT_DIMENSION offset wrong.

    This means that we're not correctly carving out the framebuffer
    memory correctly for a framebuffer allocated by EFI and
    therefore see corruption when loading amdgpu before the display
    driver takes over control of the framebuffer scanout.

    Fix this by checking the DCE_HWIP and picking the correct offset
    accordingly.

    Long-term we should expose this info from DC as GMC shouldn't
    need to know about DCN registers.

    Cc: stable@vger.kernel.org
    Signed-off-by: Harry Wentland <harry.wentland@amd.com>
    Reviewed-by: Huang Rui <ray.huang@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +++++++++++++-
    1 file changed, 13 insertions(+), 1 deletion(-)

    --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    @@ -72,6 +72,9 @@
    #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
    #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2

    +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
    +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
    +

    static const char *gfxhub_client_ids[] = {
    "CB",
    @@ -1105,6 +1108,8 @@ static unsigned gmc_v9_0_get_vbios_fb_si
    u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
    unsigned size;

    + /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
    +
    if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
    size = AMDGPU_VBIOS_VGA_ALLOCATION;
    } else {
    @@ -1113,11 +1118,18 @@ static unsigned gmc_v9_0_get_vbios_fb_si
    switch (adev->ip_versions[DCE_HWIP][0]) {
    case IP_VERSION(1, 0, 0):
    case IP_VERSION(1, 0, 1):
    - case IP_VERSION(2, 1, 0):
    viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
    size = (REG_GET_FIELD(viewport,
    HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
    REG_GET_FIELD(viewport,
    + HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
    + 4);
    + break;
    + case IP_VERSION(2, 1, 0):
    + viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
    + size = (REG_GET_FIELD(viewport,
    + HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
    + REG_GET_FIELD(viewport,
    HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
    4);
    break;

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