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    Subject[PATCH 5.10 154/563] crypto: stm32/cryp - fix CTR counter carry
    Date
    From: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>

    [ Upstream commit 41c76690b0990efacd15d35cfb4e77318cd80ebb ]

    STM32 CRYP hardware doesn't manage CTR counter bigger than max U32, as
    a workaround, at each block the current IV is saved, if the saved IV
    lower u32 is 0xFFFFFFFF, the full IV is manually incremented, and set
    in hardware.
    Fixes: bbb2832620ac ("crypto: stm32 - Fix sparse warnings")

    Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/crypto/stm32/stm32-cryp.c | 27 +++++++++++++--------------
    1 file changed, 13 insertions(+), 14 deletions(-)

    diff --git a/drivers/crypto/stm32/stm32-cryp.c b/drivers/crypto/stm32/stm32-cryp.c
    index 7389a0536ff02..d13b262b36252 100644
    --- a/drivers/crypto/stm32/stm32-cryp.c
    +++ b/drivers/crypto/stm32/stm32-cryp.c
    @@ -163,7 +163,7 @@ struct stm32_cryp {
    struct scatter_walk in_walk;
    struct scatter_walk out_walk;

    - u32 last_ctr[4];
    + __be32 last_ctr[4];
    u32 gcm_ctr;
    };

    @@ -1217,27 +1217,26 @@ static void stm32_cryp_check_ctr_counter(struct stm32_cryp *cryp)
    {
    u32 cr;

    - if (unlikely(cryp->last_ctr[3] == 0xFFFFFFFF)) {
    - cryp->last_ctr[3] = 0;
    - cryp->last_ctr[2]++;
    - if (!cryp->last_ctr[2]) {
    - cryp->last_ctr[1]++;
    - if (!cryp->last_ctr[1])
    - cryp->last_ctr[0]++;
    - }
    + if (unlikely(cryp->last_ctr[3] == cpu_to_be32(0xFFFFFFFF))) {
    + /*
    + * In this case, we need to increment manually the ctr counter,
    + * as HW doesn't handle the U32 carry.
    + */
    + crypto_inc((u8 *)cryp->last_ctr, sizeof(cryp->last_ctr));

    cr = stm32_cryp_read(cryp, CRYP_CR);
    stm32_cryp_write(cryp, CRYP_CR, cr & ~CR_CRYPEN);

    - stm32_cryp_hw_write_iv(cryp, (__be32 *)cryp->last_ctr);
    + stm32_cryp_hw_write_iv(cryp, cryp->last_ctr);

    stm32_cryp_write(cryp, CRYP_CR, cr);
    }

    - cryp->last_ctr[0] = stm32_cryp_read(cryp, CRYP_IV0LR);
    - cryp->last_ctr[1] = stm32_cryp_read(cryp, CRYP_IV0RR);
    - cryp->last_ctr[2] = stm32_cryp_read(cryp, CRYP_IV1LR);
    - cryp->last_ctr[3] = stm32_cryp_read(cryp, CRYP_IV1RR);
    + /* The IV registers are BE */
    + cryp->last_ctr[0] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR));
    + cryp->last_ctr[1] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR));
    + cryp->last_ctr[2] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR));
    + cryp->last_ctr[3] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR));
    }

    static bool stm32_cryp_irq_read_data(struct stm32_cryp *cryp)
    --
    2.34.1


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