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    Subject[PATCH 5.16 0218/1039] arm64: dts: ti: k3-am642: Fix the L2 cache sets
    Date
    From: Nishanth Menon <nm@ti.com>

    [ Upstream commit a27a93bf70045be54b594fa8482959ffb84166d7 ]

    A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
    of 64 bytes and 16-way set-associative cache structure.

    256KB of L2 / 64 (line length) = 4096 ways
    4096 ways / 16 = 256 sets

    Fix the l2 cache-sets.

    [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
    [2] https://www.ti.com/lit/pdf/spruim2

    Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
    Reported-by: Peng Fan <peng.fan@nxp.com>
    Signed-off-by: Nishanth Menon <nm@ti.com>
    Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
    Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
    Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
    index e2b397c884018..8a76f4821b11b 100644
    --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
    @@ -60,6 +60,6 @@
    cache-level = <2>;
    cache-size = <0x40000>;
    cache-line-size = <64>;
    - cache-sets = <512>;
    + cache-sets = <256>;
    };
    };
    --
    2.34.1


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