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    Subject[PATCH 5.15 706/846] PCI: pci-bridge-emul: Correctly set PCIe capabilities
    Date
    From: Pali Rohár <pali@kernel.org>

    commit 1f1050c5e1fefb34ac90a506b43e9da803b5f8f7 upstream.

    Older mvebu hardware provides PCIe Capability structure only in version 1.
    New mvebu and aardvark hardware provides it in version 2. So do not force
    version to 2 in pci_bridge_emul_init() and rather allow drivers to set
    correct version. Drivers need to set version in pcie_conf.cap field without
    overwriting PCI_CAP_LIST_ID register. Both drivers (mvebu and aardvark) do
    not provide slot support yet, so do not set PCI_EXP_FLAGS_SLOT flag.

    Link: https://lore.kernel.org/r/20211124155944.1290-6-pali@kernel.org
    Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
    Signed-off-by: Pali Rohár <pali@kernel.org>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pci/controller/pci-aardvark.c | 4 +++-
    drivers/pci/controller/pci-mvebu.c | 8 ++++++++
    drivers/pci/pci-bridge-emul.c | 5 +----
    3 files changed, 12 insertions(+), 5 deletions(-)

    --- a/drivers/pci/controller/pci-aardvark.c
    +++ b/drivers/pci/controller/pci-aardvark.c
    @@ -872,7 +872,6 @@ advk_pci_bridge_emul_pcie_conf_read(stru
    return PCI_BRIDGE_EMUL_HANDLED;
    }

    - case PCI_CAP_LIST_ID:
    case PCI_EXP_DEVCAP:
    case PCI_EXP_DEVCTL:
    *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
    @@ -953,6 +952,9 @@ static int advk_sw_pci_bridge_init(struc
    /* Support interrupt A for MSI feature */
    bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;

    + /* Aardvark HW provides PCIe Capability structure in version 2 */
    + bridge->pcie_conf.cap = cpu_to_le16(2);
    +
    /* Indicates supports for Completion Retry Status */
    bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);

    --- a/drivers/pci/controller/pci-mvebu.c
    +++ b/drivers/pci/controller/pci-mvebu.c
    @@ -573,6 +573,8 @@ static struct pci_bridge_emul_ops mvebu_
    static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
    {
    struct pci_bridge_emul *bridge = &port->bridge;
    + u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
    + u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);

    bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
    bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
    @@ -585,6 +587,12 @@ static void mvebu_pci_bridge_emul_init(s
    bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
    }

    + /*
    + * Older mvebu hardware provides PCIe Capability structure only in
    + * version 1. New hardware provides it in version 2.
    + */
    + bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
    +
    bridge->has_pcie = true;
    bridge->data = port;
    bridge->ops = &mvebu_pci_bridge_emul_ops;
    --- a/drivers/pci/pci-bridge-emul.c
    +++ b/drivers/pci/pci-bridge-emul.c
    @@ -297,10 +297,7 @@ int pci_bridge_emul_init(struct pci_brid
    if (bridge->has_pcie) {
    bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
    bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
    - /* Set PCIe v2, root port, slot support */
    - bridge->pcie_conf.cap =
    - cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
    - PCI_EXP_FLAGS_SLOT);
    + bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
    bridge->pcie_cap_regs_behavior =
    kmemdup(pcie_cap_regs_behavior,
    sizeof(pcie_cap_regs_behavior),

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