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    Subject[PATCH 5.10 250/563] powerpc/perf: MMCR0 control for PMU registers under PMCC=00
    Date
    From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>

    [ Upstream commit 91668ab7db4bcfae332e561df1de2401f3f18553 ]

    PowerISA v3.1 introduces new control bit (PMCCEXT) for restricting
    access to group B PMU registers in problem state when
    MMCR0 PMCC=0b00. In problem state and when MMCR0 PMCC=0b00,
    setting the Monitor Mode Control Register bit 54 (MMCR0 PMCCEXT),
    will restrict read permission on Group B Performance Monitor
    Registers (SIER, SIAR, SDAR and MMCR1). When this bit is set to zero,
    group B registers will be readable. In other platforms (like power9),
    the older behaviour is retained where group B PMU SPRs are readable.

    Patch adds support for MMCR0 PMCCEXT bit in power10 by enabling
    this bit during boot and during the PMU event enable/disable callback
    functions.

    Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/1606409684-1589-8-git-send-email-atrajeev@linux.vnet.ibm.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/powerpc/include/asm/reg.h | 1 +
    arch/powerpc/kernel/cpu_setup_power.c | 1 +
    arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
    arch/powerpc/perf/core-book3s.c | 4 ++++
    arch/powerpc/perf/isa207-common.c | 8 ++++++++
    5 files changed, 15 insertions(+)

    diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
    index f4b98903064f5..6afb14b6bbc26 100644
    --- a/arch/powerpc/include/asm/reg.h
    +++ b/arch/powerpc/include/asm/reg.h
    @@ -865,6 +865,7 @@
    #define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
    #define MMCR0_EBE 0x00100000UL /* Event based branch enable */
    #define MMCR0_PMCC 0x000c0000UL /* PMC control */
    +#define MMCR0_PMCCEXT ASM_CONST(0x00000200) /* PMCCEXT control */
    #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
    #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
    #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
    diff --git a/arch/powerpc/kernel/cpu_setup_power.c b/arch/powerpc/kernel/cpu_setup_power.c
    index 0c2191ee139ec..3cca88ee96d71 100644
    --- a/arch/powerpc/kernel/cpu_setup_power.c
    +++ b/arch/powerpc/kernel/cpu_setup_power.c
    @@ -123,6 +123,7 @@ static void init_PMU_ISA31(void)
    {
    mtspr(SPRN_MMCR3, 0);
    mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
    + mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
    }

    /*
    diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
    index 1098863e17ee8..9d079659b24d3 100644
    --- a/arch/powerpc/kernel/dt_cpu_ftrs.c
    +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
    @@ -454,6 +454,7 @@ static void init_pmu_power10(void)

    mtspr(SPRN_MMCR3, 0);
    mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
    + mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
    }

    static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
    diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
    index 91452313489f1..7bda7499d0401 100644
    --- a/arch/powerpc/perf/core-book3s.c
    +++ b/arch/powerpc/perf/core-book3s.c
    @@ -95,6 +95,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
    #define SPRN_SIER3 0
    #define MMCRA_SAMPLE_ENABLE 0
    #define MMCRA_BHRB_DISABLE 0
    +#define MMCR0_PMCCEXT 0

    static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
    {
    @@ -1245,6 +1246,9 @@ static void power_pmu_disable(struct pmu *pmu)
    val |= MMCR0_FC;
    val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
    MMCR0_FC56);
    + /* Set mmcr0 PMCCEXT for p10 */
    + if (ppmu->flags & PPMU_ARCH_31)
    + val |= MMCR0_PMCCEXT;

    /*
    * The barrier is to make sure the mtspr has been
    diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
    index 5e8eedda45d39..58448f0e47213 100644
    --- a/arch/powerpc/perf/isa207-common.c
    +++ b/arch/powerpc/perf/isa207-common.c
    @@ -561,6 +561,14 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
    if (!(pmc_inuse & 0x60))
    mmcr->mmcr0 |= MMCR0_FC56;

    + /*
    + * Set mmcr0 (PMCCEXT) for p10 which
    + * will restrict access to group B registers
    + * when MMCR0 PMCC=0b00.
    + */
    + if (cpu_has_feature(CPU_FTR_ARCH_31))
    + mmcr->mmcr0 |= MMCR0_PMCCEXT;
    +
    mmcr->mmcr1 = mmcr1;
    mmcr->mmcra = mmcra;
    mmcr->mmcr2 = mmcr2;
    --
    2.34.1


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