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    Subject[PATCH v4 10/16] clk: samsung: fsd: Add cam_csi block clock information
    Date
    Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work.

    Cc: linux-fsd@tesla.com
    Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
    Signed-off-by: Sathyakam M <sathya@samsung.com>
    Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
    Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
    ---
    drivers/clk/samsung/clk-fsd.c | 207 ++++++++++++++++++++++++++++++++++
    1 file changed, 207 insertions(+)

    diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
    index f9c4b4c5e0cb..5d009c70e97d 100644
    --- a/drivers/clk/samsung/clk-fsd.c
    +++ b/drivers/clk/samsung/clk-fsd.c
    @@ -1545,6 +1545,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
    .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
    };

    +/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
    +#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
    +#define PLL_CON0_PLL_CAM_CSI 0x100
    +#define DIV_CAM_CSI0_ACLK 0x1800
    +#define DIV_CAM_CSI1_ACLK 0x1804
    +#define DIV_CAM_CSI2_ACLK 0x1808
    +#define DIV_CAM_CSI_BUSD 0x180c
    +#define DIV_CAM_CSI_BUSP 0x1810
    +#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
    +#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
    +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
    +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
    +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
    +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
    +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
    +#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
    +#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
    +#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
    +#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
    +#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
    +#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
    +#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
    +#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
    +#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
    +#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
    +#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
    +#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
    +#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
    +#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
    +#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
    +#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
    +#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
    +#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
    +#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
    +#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
    +#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
    +#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
    +#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
    +#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
    +#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
    +#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
    +#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
    +#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
    +
    +static const unsigned long cam_csi_clk_regs[] __initconst = {
    + PLL_LOCKTIME_PLL_CAM_CSI,
    + PLL_CON0_PLL_CAM_CSI,
    + DIV_CAM_CSI0_ACLK,
    + DIV_CAM_CSI1_ACLK,
    + DIV_CAM_CSI2_ACLK,
    + DIV_CAM_CSI_BUSD,
    + DIV_CAM_CSI_BUSP,
    + GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
    + GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
    + GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
    + GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
    + GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
    + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
    + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
    + GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
    + GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
    +};
    +
    +static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
    + PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
    +};
    +
    +static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
    + PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
    + PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
    +};
    +
    +PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
    +
    +static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
    + MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
    +};
    +
    +static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
    + DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
    + DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
    + DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
    + DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
    + DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
    +};
    +
    +static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
    + GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
    + GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
    + CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
    + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
    + GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
    + GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
    + GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
    + GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
    + GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
    + GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
    + GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
    + GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
    + GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
    + GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
    + GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
    + GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
    + GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
    + "dout_cam_csi_busd",
    + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
    + CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
    + "dout_cam_csi_busp",
    + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
    + CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
    + GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
    + GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
    + GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
    +};
    +
    +static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
    + .pll_clks = cam_csi_pll_clks,
    + .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
    + .mux_clks = cam_csi_mux_clks,
    + .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
    + .div_clks = cam_csi_div_clks,
    + .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
    + .gate_clks = cam_csi_gate_clks,
    + .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
    + .nr_clk_ids = CAM_CSI_NR_CLK,
    + .clk_regs = cam_csi_clk_regs,
    + .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
    +};
    +
    /**
    * fsd_cmu_probe - Probe function for FSD platform clocks
    * @pdev: Pointer to platform device
    @@ -1576,6 +1780,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
    }, {
    .compatible = "tesla,fsd-clock-mfc",
    .data = &mfc_cmu_info,
    + }, {
    + .compatible = "tesla,fsd-clock-cam_csi",
    + .data = &cam_csi_cmu_info,
    }, {
    },
    };
    --
    2.25.1
    \
     
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      Last update: 2022-01-23 20:21    [W:4.052 / U:0.052 seconds]
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