Messages in this thread | | | From | Vitaly Wool <> | Date | Thu, 20 Jan 2022 16:37:00 +0100 | Subject | Re: |
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Hey,
On Thu, Jan 20, 2022 at 4:30 PM Myrtle Shah <gatecat@ds0.me> wrote: > > These are some initial patches to bugs I found attempting to > get a XIP kernel working on hardware: > - 32-bit VexRiscv processor > - kernel in SPI flash, at 0x00200000 > - 16MB of RAM at 0x10000000 > - MMU enabled > > I still have some more debugging to do, but these at least > get the kernel as far as initialising the MMU, and I would > appreciate feedback if anyone else is working on RISC-V XIP.
I'll try to support you as much as I can, unfortunately I don't have any 32-bit RISC-V around so I was rather thinking of extending the RISC-V XIP support to 64-bit non-MMU targets. For now just please keep in mind that there might be some inherent assumptions that a target is 64 bit.
Best regards, Vitaly
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