Messages in this thread | | | Date | Thu, 20 Jan 2022 16:23:52 +0530 | Subject | Re: [PATCH 3/4] arm64: dts: qcom: sm8150: Add pdc interrupt controller node | From | Maulik Shah <> |
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Hi,
On 1/20/2022 2:01 AM, Bhupesh Sharma wrote: > Add pdc interrupt controller for sm8150. > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: Rob Herring <robh@kernel.org> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 6012322a5984..cc4dc11b2585 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 { > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > }; > > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm8150-pdc", "qcom,pdc"; > + reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>;
<0x17c000f0 0x64>;
Remove the second reg, its not used in the driver and also not documented yet.
Thanks, Maulik > + qcom,pdc-ranges = <0 480 94>, <94 609 31>, > + <125 63 1>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > ufs_mem_hc: ufshc@1d84000 { > compatible = "qcom,sm8150-ufshc", "qcom,ufshc", > "jedec,ufs-2.0";
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