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Subject[RFC PATCH v2 3/5] mtd: rawnand: gpmi: use a table to get EDO mode setup
Date
This is a preparation patch for the upcoming validation of the
GPMI controller clock rate.

Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

---

Changes in v2:
- Add the patch to the series.

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 43 +++++++++++++++-------
1 file changed, 30 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
index 73c3bf59b55e..4ac695aa5131 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
@@ -570,6 +570,27 @@ static int bch_set_geometry(struct gpmi_nand_data *this)
return ret;
}

+struct edo_mode {
+ u32 tRC_min;
+ long clk_rate;
+ u8 wrn_dly_sel;
+};
+
+static const struct edo_mode edo_modes[] = {
+ {.tRC_min = 30000, .clk_rate = 22000000,
+ .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS},
+ {.tRC_min = 30000, .clk_rate = 22000000,
+ .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS},
+ {.tRC_min = 30000, .clk_rate = 22000000,
+ .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS},
+ {.tRC_min = 30000, .clk_rate = 22000000,
+ .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS},
+ {.tRC_min = 25000, .clk_rate = 80000000,
+ .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY},
+ {.tRC_min = 20000, .clk_rate = 100000000,
+ .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY},
+};
+
/*
* <1> Firstly, we should know what's the GPMI-clock means.
* The GPMI-clock is the internal clock in the gpmi nand controller.
@@ -657,22 +678,18 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
int sample_delay_ps, sample_delay_factor;
u16 busy_timeout_cycles;
u8 wrn_dly_sel;
+ int i, emode = ARRAY_SIZE(edo_modes) - 1;

- if (sdr->tRC_min >= 30000) {
- /* ONFI non-EDO modes [0-3] */
- hw->clk_rate = 22000000;
- wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
- } else if (sdr->tRC_min >= 25000) {
- /* ONFI EDO mode 4 */
- hw->clk_rate = 80000000;
- wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
- } else {
- /* ONFI EDO mode 5 */
- hw->clk_rate = 100000000;
- wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
+ /* Search the required EDO mode */
+ for (i = 0; i < ARRAY_SIZE(edo_modes); i++) {
+ if (sdr->tRC_min >= edo_modes[i].tRC_min) {
+ emode = i;
+ break;
+ }
}

- hw->clk_rate = clk_round_rate(r->clock[0], hw->clk_rate);
+ hw->clk_rate = clk_round_rate(r->clock[0], edo_modes[emode].clk_rate);
+ wrn_dly_sel = edo_modes[emode].wrn_dly_sel;

/* SDR core timings are given in picoseconds */
period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate);
--
2.32.0
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