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    Subject[PATCH 11/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks
    Date
    Add missing CryptoEngine clocks and pll11 required clock.

    Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
    ---
    drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++
    1 file changed, 244 insertions(+)

    diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
    index 0923d7f79a1c..46d0fe511868 100644
    --- a/drivers/clk/qcom/gcc-ipq806x.c
    +++ b/drivers/clk/qcom/gcc-ipq806x.c
    @@ -268,6 +268,24 @@ static struct clk_pll pll18 = {
    },
    };

    +static struct clk_pll pll11 = {
    + .l_reg = 0x3184,
    + .m_reg = 0x3188,
    + .n_reg = 0x318c,
    + .config_reg = 0x3194,
    + .mode_reg = 0x3180,
    + .status_reg = 0x3198,
    + .status_bit = 16,
    + .clkr.hw.init = &(struct clk_init_data){
    + .name = "pll11",
    + .parent_data = &(const struct clk_parent_data){
    + .fw_name = "pxo",
    + },
    + .num_parents = 1,
    + .ops = &clk_pll_ops,
    + },
    +};
    +
    enum {
    P_PXO,
    P_PLL8,
    @@ -276,6 +294,7 @@ enum {
    P_CXO,
    P_PLL14,
    P_PLL18,
    + P_PLL11,
    };

    static const struct parent_map gcc_pxo_pll8_map[] = {
    @@ -343,6 +362,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
    { .hw = &pll18.clkr.hw },
    };

    +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
    + { P_PXO, 0 },
    + { P_PLL8, 4 },
    + { P_PLL0, 2 },
    + { P_PLL14, 5 },
    + { P_PLL18, 1 },
    + { P_PLL11, 3 },
    +};
    +
    +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
    + { .fw_name = "pxo" },
    + { .hw = &pll8_vote.hw },
    + { .hw = &pll0_vote.hw },
    + { .hw = &pll14.clkr.hw },
    + { .hw = &pll18.clkr.hw },
    + { .hw = &pll11.clkr.hw },
    +
    +};
    +
    +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
    + { P_PXO, 0 },
    + { P_PLL3, 6 },
    + { P_PLL0, 2 },
    + { P_PLL14, 5 },
    + { P_PLL18, 1 },
    + { P_PLL11, 3 },
    +};
    +
    +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
    + { .fw_name = "pxo" },
    + { .hw = &pll3.clkr.hw },
    + { .hw = &pll0_vote.hw },
    + { .hw = &pll14.clkr.hw },
    + { .hw = &pll18.clkr.hw },
    + { .hw = &pll11.clkr.hw },
    +
    +};
    +
    static struct freq_tbl clk_tbl_gsbi_uart[] = {
    { 1843200, P_PLL8, 2, 6, 625 },
    { 3686400, P_PLL8, 2, 12, 625 },
    @@ -2832,6 +2889,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
    },
    };

    +static const struct freq_tbl clk_tbl_ce5_core[] = {
    + { 150000000, P_PLL3, 8, 1, 1 },
    + { 213200000, P_PLL11, 5, 1, 1 },
    + { }
    +};
    +
    +static struct clk_dyn_rcg ce5_core_src = {
    + .ns_reg[0] = 0x36C4,
    + .ns_reg[1] = 0x36C8,
    + .bank_reg = 0x36C0,
    + .s[0] = {
    + .src_sel_shift = 0,
    + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
    + },
    + .s[1] = {
    + .src_sel_shift = 0,
    + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
    + },
    + .p[0] = {
    + .pre_div_shift = 3,
    + .pre_div_width = 4,
    + },
    + .p[1] = {
    + .pre_div_shift = 3,
    + .pre_div_width = 4,
    + },
    + .mux_sel_bit = 0,
    + .freq_tbl = clk_tbl_ce5_core,
    + .clkr = {
    + .enable_reg = 0x36C0,
    + .enable_mask = BIT(1),
    + .hw.init = &(struct clk_init_data){
    + .name = "ce5_core_src",
    + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
    + .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
    + .ops = &clk_dyn_rcg_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch ce5_core_clk = {
    + .halt_reg = 0x2FDC,
    + .halt_bit = 5,
    + .hwcg_reg = 0x36CC,
    + .hwcg_bit = 6,
    + .clkr = {
    + .enable_reg = 0x36CC,
    + .enable_mask = BIT(4),
    + .hw.init = &(struct clk_init_data){
    + .name = "ce5_core_clk",
    + .parent_hws = (const struct clk_hw*[]){
    + &ce5_core_src.clkr.hw,
    + },
    + .num_parents = 1,
    + .ops = &clk_branch_ops,
    + .flags = CLK_SET_RATE_PARENT,
    + },
    + },
    +};
    +
    +static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
    + { 160000000, P_PLL0, 5, 1, 1 },
    + { 213200000, P_PLL11, 5, 1, 1 },
    + { }
    +};
    +
    +static struct clk_dyn_rcg ce5_a_clk_src = {
    + .ns_reg[0] = 0x3d84,
    + .ns_reg[1] = 0x3d88,
    + .bank_reg = 0x3d80,
    + .s[0] = {
    + .src_sel_shift = 0,
    + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
    + },
    + .s[1] = {
    + .src_sel_shift = 0,
    + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
    + },
    + .p[0] = {
    + .pre_div_shift = 3,
    + .pre_div_width = 4,
    + },
    + .p[1] = {
    + .pre_div_shift = 3,
    + .pre_div_width = 4,
    + },
    + .mux_sel_bit = 0,
    + .freq_tbl = clk_tbl_ce5_a_clk,
    + .clkr = {
    + .enable_reg = 0x3d80,
    + .enable_mask = BIT(1),
    + .hw.init = &(struct clk_init_data){
    + .name = "ce5_a_clk_src",
    + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
    + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
    + .ops = &clk_dyn_rcg_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch ce5_a_clk = {
    + .halt_reg = 0x3c20,
    + .halt_bit = 12,
    + .hwcg_reg = 0x3d8c,
    + .hwcg_bit = 6,
    + .clkr = {
    + .enable_reg = 0x3d8c,
    + .enable_mask = BIT(4),
    + .hw.init = &(struct clk_init_data){
    + .name = "ce5_a_clk",
    + .parent_hws = (const struct clk_hw*[]){
    + &ce5_a_clk_src.clkr.hw,
    + },
    + .num_parents = 1,
    + .ops = &clk_branch_ops,
    + .flags = CLK_SET_RATE_PARENT,
    + },
    + },
    +};
    +
    +static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
    + { 160000000, P_PLL0, 5, 1, 1 },
    + { 213200000, P_PLL11, 5, 1, 1 },
    + { }
    +};
    +
    +static struct clk_dyn_rcg ce5_h_clk_src = {
    + .ns_reg[0] = 0x3c64,
    + .ns_reg[1] = 0x3c68,
    + .bank_reg = 0x3c60,
    + .s[0] = {
    + .src_sel_shift = 0,
    + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
    + },
    + .s[1] = {
    + .src_sel_shift = 0,
    + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
    + },
    + .p[0] = {
    + .pre_div_shift = 3,
    + .pre_div_width = 4,
    + },
    + .p[1] = {
    + .pre_div_shift = 3,
    + .pre_div_width = 4,
    + },
    + .mux_sel_bit = 0,
    + .freq_tbl = clk_tbl_ce5_h_clk,
    + .clkr = {
    + .enable_reg = 0x3c60,
    + .enable_mask = BIT(1),
    + .hw.init = &(struct clk_init_data){
    + .name = "ce5_h_clk_src",
    + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
    + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
    + .ops = &clk_dyn_rcg_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch ce5_h_clk = {
    + .halt_reg = 0x3c20,
    + .halt_bit = 11,
    + .hwcg_reg = 0x3c6c,
    + .hwcg_bit = 6,
    + .clkr = {
    + .enable_reg = 0x3c6c,
    + .enable_mask = BIT(4),
    + .hw.init = &(struct clk_init_data){
    + .name = "ce5_h_clk",
    + .parent_hws = (const struct clk_hw*[]){
    + &ce5_h_clk_src.clkr.hw,
    + },
    + .num_parents = 1,
    + .ops = &clk_branch_ops,
    + .flags = CLK_SET_RATE_PARENT,
    + },
    + },
    +};
    +
    static struct clk_regmap *gcc_ipq806x_clks[] = {
    [PLL0] = &pll0.clkr,
    [PLL0_VOTE] = &pll0_vote,
    @@ -2839,6 +3076,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
    [PLL4_VOTE] = &pll4_vote,
    [PLL8] = &pll8.clkr,
    [PLL8_VOTE] = &pll8_vote,
    + [PLL11] = &pll11.clkr,
    [PLL14] = &pll14.clkr,
    [PLL14_VOTE] = &pll14_vote,
    [PLL18] = &pll18.clkr,
    @@ -2953,6 +3191,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
    [PLL9] = &hfpll0.clkr,
    [PLL10] = &hfpll1.clkr,
    [PLL12] = &hfpll_l2.clkr,
    + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
    + [CE5_A_CLK] = &ce5_a_clk.clkr,
    + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
    + [CE5_H_CLK] = &ce5_h_clk.clkr,
    + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
    + [CE5_CORE_CLK] = &ce5_core_clk.clkr,
    };

    static const struct qcom_reset_map gcc_ipq806x_resets[] = {
    --
    2.33.1
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      Last update: 2022-01-18 02:03    [W:2.261 / U:0.060 seconds]
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