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SubjectRe: [PATCH v2] pwm: meson: external clock configuration for s4
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On Fri 14 Jan 2022 at 17:07, <Jiayi.Zhou@amlogic.com> wrote:

> From: "Jiayi.zhou" <jiayi.zhou@amlogic.com>
>
> For PWM controller in the Meson-S4 SoC,
> PWM needs to obtain an external clock source.
> This patch tries to describe them in the DT compatible data.
>

I'm sorry but I have already commented on v1 that all the mess in here
don't seem necessary. For Reference:

"""
You trying to bypass the input selection mux. There is no reason to do
so.

Your input clocks should be
* OSC
* vid_pll
* fdiv3
* fdiv4

While the pwm driver could welcome a rework around how it deal with DT
and the clocks, this S4 chip does not warrant any change compared to
previous generation (AFAICT)

All the stuff around "extern_clk" should go away IMO.
"""

Unless you can *really* justify why this approach is required, it is
firm Nack.

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