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    Subject[PATCH v17 3/4] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
    Date
    From: Kuogee Hsieh <khsieh@codeaurora.org>

    Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
    This patch will use tps4 to perform link training #2 if sinker's DPCD
    supports it.

    Changes in V2:
    -- replace dp_catalog_ctrl_set_pattern() with dp_catalog_ctrl_set_pattern_state_bit()

    Changes in V3:
    -- change state_ctrl_bits type to u32 and pattern type to u8

    Changes in V4:
    -- align } else if { and } else {

    Changes in v10:
    -- group into one series

    Changes in v11:
    -- drop drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read

    Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>

    Reviewed-by: Stephen Boyd <swboyd@chromium.org>
    ---
    drivers/gpu/drm/msm/dp/dp_catalog.c | 12 ++++++------
    drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +-
    drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 ++++++++++++-----
    3 files changed, 19 insertions(+), 12 deletions(-)

    diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
    index 6ae9b29..64f0b26 100644
    --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
    +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
    @@ -456,19 +456,19 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
    dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0);
    }

    -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog,
    - u32 pattern)
    +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog,
    + u32 state_bit)
    {
    int bit, ret;
    u32 data;
    struct dp_catalog_private *catalog = container_of(dp_catalog,
    struct dp_catalog_private, dp_catalog);

    - bit = BIT(pattern - 1);
    - DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, pattern);
    + bit = BIT(state_bit - 1);
    + DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, state_bit);
    dp_catalog_ctrl_state_ctrl(dp_catalog, bit);

    - bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;
    + bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;

    /* Poll for mainlink ready status */
    ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base +
    @@ -476,7 +476,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog,
    data, data & bit,
    POLLING_SLEEP_US, POLLING_TIMEOUT_US);
    if (ret < 0) {
    - DRM_ERROR("set pattern for link_train=%d failed\n", pattern);
    + DRM_ERROR("set state_bit for link_train=%d failed\n", state_bit);
    return ret;
    }
    return 0;
    diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
    index 6965afa..7dea101 100644
    --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
    +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
    @@ -94,7 +94,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
    void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
    void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
    u32 stream_rate_khz, bool fixed_nvid);
    -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern);
    +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern);
    void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);
    bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog);
    void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
    diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
    index 9c80b49..f98df93 100644
    --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
    +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
    @@ -1083,7 +1083,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,

    *training_step = DP_TRAINING_1;

    - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1);
    + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
    if (ret)
    return ret;
    dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
    @@ -1181,7 +1181,8 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
    int *training_step)
    {
    int tries = 0, ret = 0;
    - char pattern;
    + u8 pattern;
    + u32 state_ctrl_bit;
    int const maximum_retries = 5;
    u8 link_status[DP_LINK_STATUS_SIZE];

    @@ -1189,12 +1190,18 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,

    *training_step = DP_TRAINING_2;

    - if (drm_dp_tps3_supported(ctrl->panel->dpcd))
    + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
    + pattern = DP_TRAINING_PATTERN_4;
    + state_ctrl_bit = 4;
    + } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
    pattern = DP_TRAINING_PATTERN_3;
    - else
    + state_ctrl_bit = 3;
    + } else {
    pattern = DP_TRAINING_PATTERN_2;
    + state_ctrl_bit = 2;
    + }

    - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern);
    + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
    if (ret)
    return ret;

    --
    The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
    a Linux Foundation Collaborative Project
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