Messages in this thread | | | Subject | Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver | From | Neil Armstrong <> | Date | Wed, 12 Jan 2022 09:19:35 +0100 |
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Hi,
On 12/01/2022 08:24, Jagan Teki wrote: > Hi Neil, > > On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong <narmstrong@baylibre.com> wrote: >> >> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom >> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other >> Amlogic SoCs. >> >> This adds support for the Glue managing the transceiver, mimicing the init flow provided >> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the >> Analog PHY in the proper way. >> >> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock >> is derived and feeds the ENCL encoder and the VIU pixel reader. >> >> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the >> DW-MIPI-DSI transceiver. >> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> ---
[..]
>> + >> +static const struct component_ops meson_dw_mipi_dsi_ops = { >> + .bind = meson_dw_mipi_dsi_bind, >> + .unbind = meson_dw_mipi_dsi_unbind, >> +}; > > Do you thought of non-component based meson DSI like STM DSI? It > require changes from meson drm but just to understand if you have any > such plan.
I have no such plans for now, note this serie has been rewritten at [1] but still with based with components.
If worth it, the plan is to get it with components and than yes if it's simpler drop components completely.
I'll have a look at how ST does
Neil
[1] https://lore.kernel.org/r/20220107145515.613009-1-narmstrong@baylibre.com
> > Thanks, > Jagan. >
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