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    Subject[PATCH AUTOSEL 5.14 095/252] drm/msm/a6xx: Fix llcc configuration for a660 gpu
    Date
    From: Akhil P Oommen <akhilpo@codeaurora.org>

    [ Upstream commit a6f24383f6c0a8d64d1f6afa10733ae4e8f236e0 ]

    Add the missing scache_cntl0 register programing which is required for
    a660 gpu.

    Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
    Link: https://lore.kernel.org/r/20210730011945.v4.1.I110b87677ef16d97397fb7c81c07a16e1f5d211e@changeid
    Signed-off-by: Rob Clark <robdclark@chromium.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++++++++++++++++-----------
    1 file changed, 27 insertions(+), 19 deletions(-)

    diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
    index 9c5e4618aa0a..183b9f9c1b31 100644
    --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
    +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
    @@ -1383,13 +1383,13 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
    {
    struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
    struct msm_gpu *gpu = &adreno_gpu->base;
    - u32 cntl1_regval = 0;
    + u32 gpu_scid, cntl1_regval = 0;

    if (IS_ERR(a6xx_gpu->llc_mmio))
    return;

    if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
    - u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
    + gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);

    gpu_scid &= 0x1f;
    cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
    @@ -1409,26 +1409,34 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
    }
    }

    - if (cntl1_regval) {
    + if (!cntl1_regval)
    + return;
    +
    + /*
    + * Program the slice IDs for the various GPU blocks and GPU MMU
    + * pagetables
    + */
    + if (!a6xx_gpu->have_mmu500) {
    + a6xx_llc_write(a6xx_gpu,
    + REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
    +
    /*
    - * Program the slice IDs for the various GPU blocks and GPU MMU
    - * pagetables
    + * Program cacheability overrides to not allocate cache
    + * lines on a write miss
    */
    - if (a6xx_gpu->have_mmu500)
    - gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0),
    - cntl1_regval);
    - else {
    - a6xx_llc_write(a6xx_gpu,
    - REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
    -
    - /*
    - * Program cacheability overrides to not allocate cache
    - * lines on a write miss
    - */
    - a6xx_llc_rmw(a6xx_gpu,
    - REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
    - }
    + a6xx_llc_rmw(a6xx_gpu,
    + REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
    + return;
    }
    +
    + gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
    +
    + /* On A660, the SCID programming for UCHE traffic is done in
    + * A6XX_GBIF_SCACHE_CNTL0[14:10]
    + */
    + if (adreno_is_a660(adreno_gpu))
    + gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
    + (1 << 8), (gpu_scid << 10) | (1 << 8));
    }

    static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
    --
    2.30.2
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