Messages in this thread | | | Date | Thu, 9 Sep 2021 09:25:30 +0200 | From | Peter Zijlstra <> | Subject | Re: [tip:locking/core] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire |
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On Wed, Sep 08, 2021 at 09:08:33AM -0700, Linus Torvalds wrote:
> So if this is purely a RISC-V thing,
Just to clarify, I think the current RISC-V thing is stonger than PowerPC, but maybe not as strong as say ARM64, but RISC-V memory ordering is still somewhat hazy to me.
Specifically, the sequence:
/* critical section s */ WRITE_ONCE(x, 1); FENCE RW, W WRITE_ONCE(s.lock, 0); /* store S */ AMOSWAP %0, 1, r.lock /* store R */ FENCE R, RW WRITE_ONCE(y, 1); /* critical section r */
fully separates section s from section r, as in RW->RW ordering (possibly not as strong as smp_mb() though), while on PowerPC it would only impose TSO ordering between sections.
The AMOSWAP is a RmW and as such matches the W from the RW->W fence, similarly it marches the R from the R->RW fence, yielding an:
RW-> W RmW R ->RW
ordering. It's the stores S and R that can be re-ordered, but not the sections themselves (same on PowerPC and many others).
Clarification from a RISC-V enabled person would be appreciated.
> then I think it's entirely reasonable to > > spin_unlock(&r); > spin_lock(&s); > > cannot be reordered.
I'm obviously completely in favour of that :-)
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