Messages in this thread Patch in this message | | | From | Kajol Jain <> | Subject | [PATCH 2/3] perf: Add macros to specify onchip L2/L3 accesses | Date | Sat, 4 Sep 2021 12:19:31 +0530 |
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Add couple of new macros to represent onchip L2 and onchip L3 accesses. Patch also adds the decoding strings in the mem_lvlnum data structure.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com> --- tools/include/uapi/linux/perf_event.h | 4 +++- tools/perf/util/mem-events.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index f92880a15645..030b3e990ac3 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -1265,7 +1265,9 @@ union perf_mem_data_src { #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ -/* 5-0xa available */ +#define PERF_MEM_LVLNUM_OC_L2 0x05 /* On Chip L2 */ +#define PERF_MEM_LVLNUM_OC_L3 0x06 /* On Chip L3 */ +/* 7-0xa available */ #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index f0e75df72b80..f846a91220c2 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -294,6 +294,8 @@ static const char * const mem_lvl[] = { }; static const char * const mem_lvlnum[] = { + [PERF_MEM_LVLNUM_OC_L2] = "OnChip L2", + [PERF_MEM_LVLNUM_OC_L3] = "OnChip L3", [PERF_MEM_LVLNUM_ANY_CACHE] = "Any cache", [PERF_MEM_LVLNUM_LFB] = "LFB", [PERF_MEM_LVLNUM_RAM] = "RAM", -- 2.26.2
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