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    Subject[PATCH v13 33/35] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x
    Date
    Memory access must be blocked before hardware reset is asserted and before
    power is gated, otherwise a serious hardware fault is inevitable. Add
    reset for memory clients to the GR2D, GR3D and Host1x nodes.

    Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
    Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
    Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
    ---
    arch/arm/boot/dts/tegra20.dtsi | 12 ++++++------
    1 file changed, 6 insertions(+), 6 deletions(-)

    diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
    index ce38055a8952..eb6e5518fb5f 100644
    --- a/arch/arm/boot/dts/tegra20.dtsi
    +++ b/arch/arm/boot/dts/tegra20.dtsi
    @@ -40,8 +40,8 @@ host1x@50000000 {
    interrupt-names = "syncpt", "host1x";
    clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
    clock-names = "host1x";
    - resets = <&tegra_car 28>;
    - reset-names = "host1x";
    + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
    + reset-names = "host1x", "mc";
    operating-points-v2 = <&host1x_dvfs_opp_table>;
    power-domains = <&pd_core>;

    @@ -98,8 +98,8 @@ gr2d@54140000 {
    reg = <0x54140000 0x00040000>;
    interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&tegra_car TEGRA20_CLK_GR2D>;
    - resets = <&tegra_car 21>;
    - reset-names = "2d";
    + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
    + reset-names = "2d", "mc";
    operating-points-v2 = <&gr2d_dvfs_opp_table>;
    power-domains = <&pd_core>;
    };
    @@ -108,8 +108,8 @@ gr3d@54180000 {
    compatible = "nvidia,tegra20-gr3d";
    reg = <0x54180000 0x00040000>;
    clocks = <&tegra_car TEGRA20_CLK_GR3D>;
    - resets = <&tegra_car 24>;
    - reset-names = "3d";
    + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
    + reset-names = "3d", "mc";
    operating-points-v2 = <&gr3d_dvfs_opp_table>;
    power-domains = <&pd_3d>;
    };
    --
    2.32.0
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