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Subject[PATCH V2 2/2] dt-bindings: riscv: Add svpbmt in cpu mmu-type property
Date
From: Guo Ren <guoren@linux.alibaba.com>

Previous patch has added svpbmt in arch/riscv and changed the
DT mmu-type. Update dt-bindings related property here.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e534f6a7cfa1..5eea9b47dfc6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -48,15 +48,18 @@ properties:

mmu-type:
description:
- Identifies the MMU address translation mode used on this
- hart. These values originate from the RISC-V Privileged
- Specification document, available from
+ Identifies the MMU address translation mode and page based
+ memory type used on used on this hart. These values originate
+ from the RISC-V Privileged Specification document, available
+ from
https://riscv.org/specifications/
$ref: "/schemas/types.yaml#/definitions/string"
enum:
- riscv,sv32
- riscv,sv39
+ - riscv,sv39,svpbmt
- riscv,sv48
+ - riscv,sv48,svpbmt
- riscv,none

riscv,isa:
--
2.25.1
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