Messages in this thread | | | From | Linus Walleij <> | Date | Thu, 23 Sep 2021 23:42:53 +0200 | Subject | Re: [RFC PATCH v2 1/4] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller |
| |
On Tue, Sep 21, 2021 at 9:30 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add DT bindings for the Renesas RZ/G2L Interrupt Controller. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> (...) > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
It is not custom to code all the interrupts into the device tree if this a one-to-one mapping, instead the hardware driver is supposed to know which IRQs to pick in the 1-to-1 map based on the compatible string, which should be unique per-SoC.
Yours, Linus Walleij
| |