Messages in this thread Patch in this message | | | From | Srinivasa Rao Mandadapu <> | Subject | [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values | Date | Wed, 22 Sep 2021 18:01:17 +0530 |
| |
Update mic control register default values to hardware reset values
Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for lpass tx macro)
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> --- sound/soc/codecs/lpass-tx-macro.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index e980b2e..66c39fb 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -279,7 +279,7 @@ static const struct reg_default tx_defaults[] = { { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, { CDC_TX_TOP_CSR_ANC_CFG, 0x00}, - { CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, + { CDC_TX_TOP_CSR_SWR_CTRL, 0x60}, { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, { CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, @@ -290,8 +290,8 @@ static const struct reg_default tx_defaults[] = { { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, - { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, - { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, + { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x0E}, + { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x0E}, { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
| |