Messages in this thread | | | Subject | Re: [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range | From | Anshuman Khandual <> | Date | Wed, 22 Sep 2021 16:29:09 +0530 |
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On 9/21/21 7:11 PM, Suzuki K Poulose wrote: > Arm Neoverse-N2 and Cortex-A710 cores are affected by an erratum where the > trbe, under some circumstances, might write upto 64bytes to an address after > the Limit as programmed by the TRBLIMITR_EL1.LIMIT. This might - > > - Corrupt a page in the ring buffer, which may corrupt trace from a > previous session, consumed by userspace. > - Hit the guard page at the end of the vmalloc area and raise a fault. > > To keep the handling simpler, we always leave the last page from the > range, which TRBE is allowed to write. This can be achieved by ensuring > that we always have more than a PAGE worth space in the range, while > calculating the LIMIT for TRBE. And then the LIMIT pointer can be adjusted > to leave the PAGE (TRBLIMITR.LIMIT -= PAGE_SIZE), out of the TRBE range > while enabling it. This makes sure that the TRBE will only write to an area > within its allowed limit (i.e, [head-head+size]) and we do not have to handle > address faults within the driver. > > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
> --- > arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++++++++ > arch/arm64/tools/cpucaps | 1 + > 2 files changed, 21 insertions(+) > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index bdbeac75ead6..e2978b89d4b8 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -364,6 +364,18 @@ static const struct midr_range tsb_flush_fail_cpus[] = { > }; > #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ > > +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > +static struct midr_range trbe_write_out_of_range_cpus[] = { > +#ifdef CONFIG_ARM64_ERRATUM_2253138 > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2224489 > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > +#endif > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -577,6 +589,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, > ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > + { > + .desc = "ARM erratum 2253138 or 2224489", > + .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > + CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 2102e15af43d..90628638e0f9 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -55,6 +55,7 @@ WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > +WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > WORKAROUND_CAVIUM_23154 > WORKAROUND_CAVIUM_27456 > WORKAROUND_CAVIUM_30115 >
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