Messages in this thread | | | Subject | Re: [PATCH 3/7] ASoC: codecs: tx-macro: Change mic control registers to volatile | From | Srinivasa Rao Mandadapu <> | Date | Tue, 21 Sep 2021 18:32:09 +0530 |
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On 9/21/2021 2:18 PM, Srinivas Kandagatla wrote: > > > On 21/09/2021 08:30, Srinivasa Rao Mandadapu wrote: >> >> On 9/20/2021 6:54 PM, Srinivas Kandagatla wrote: >> Thanks for your time Srini!! >>> >>> On 20/09/2021 08:35, Srinivasa Rao Mandadapu wrote: >>>> Update amic and dmic related tx macro control registers to volatile >>>> >>>> Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for >>>> lpass tx macro) >>>> >>>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> >>>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> >>>> --- >>>> sound/soc/codecs/lpass-tx-macro.c | 13 +++++++++++++ >>>> 1 file changed, 13 insertions(+) >>>> >>>> diff --git a/sound/soc/codecs/lpass-tx-macro.c >>>> b/sound/soc/codecs/lpass-tx-macro.c >>>> index 9273724..e65b592 100644 >>>> --- a/sound/soc/codecs/lpass-tx-macro.c >>>> +++ b/sound/soc/codecs/lpass-tx-macro.c >>>> @@ -423,6 +423,13 @@ static bool tx_is_volatile_register(struct >>>> device *dev, unsigned int reg) >>>> case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: >>>> case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: >>>> case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: >>>> + case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: >>>> + case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: >>>> + case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL: >>>> + case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL: >>>> + case CDC_TX_CLK_RST_CTRL_SWR_CONTROL: >>>> + case CDC_TX_TOP_CSR_SWR_CTRL: >>>> + case CDC_TX0_TX_PATH_SEC7: >>> >>> Why are these marked as Volatile? >>> Can you provide some details on the issue that you are seeing? >>> >>> --srini >> >> Without volatile these registers are not reflecting in Hardware and >> playback and capture is not working. >> >> Will do recheck and keep only required registers as volatile. > > This sounds like a total hack to me, > > this might be happening in your case: > > The default values for this register are different to actual defaults. > Ex: CDC_TX_TOP_CSR_SWR_AMIC0_CTL default is 0x00 > so writing 0x0 to this register will be no-op as there is no change in > the register value as compared to default value as per regmap. > > In you case make sure the hardware default values are correctly > reflected in tx_defaults array.
The default values in tx_defaults are proper. But same value is not reflecting in Hardware, but In Cache it's reflecting set value.
> > Then setting the desired value should work. > > > --srini > > > >> >>> >>> >>>> return true; >>>> } >>>> return false; >>>> @@ -1674,6 +1681,12 @@ static int tx_macro_component_probe(struct >>>> snd_soc_component *comp) >>>> snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, >>>> 0x3F, >>>> 0x0A); >>>> + snd_soc_component_update_bits(comp, >>>> CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00); >>>> + snd_soc_component_update_bits(comp, >>>> CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00); >>>> + snd_soc_component_update_bits(comp, >>>> CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0xFF, 0x00); >>>> + snd_soc_component_update_bits(comp, >>>> CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0xFF, 0x00); >>>> + snd_soc_component_update_bits(comp, >>>> CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0xFF, 0x00); >>>> + snd_soc_component_update_bits(comp, >>>> CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0xFF, 0x00); >>>> return 0; >>>> } >>>> -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
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