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    Subject[PATCH v5 2/3] iio: imx8qxp-adc: dt-bindings: iio: adc: Add binding documentation for NXP IMX8QXP ADC
    Date
    The NXP i.MX 8QuadXPlus SOC a new ADC IP, so add
    binding documentation for NXP IMX8QXP ADC.

    Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
    ---
    v1->v2:
    *Fix some indentation issues.
    *Mark status as okay.
    *Change clock2 source.
    v3->v4:
    *Remove 'status' from examples.
    *Remove unused 'state'.
    *Remove interrupts-parent.
    *Change num of address/size-cells from 1 to 2.
    v4->v5:
    *Remove unused properties
    v1 link:
    https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210830172140.414-5-caihuoqing@baidu.com/
    v3 link:
    https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210907015724.1377-3-caihuoqing@baidu.com/
    v4 link:
    https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210912071334.1745-3-caihuoqing@baidu.com/

    .../bindings/iio/adc/nxp,imx8qxp-adc.yaml | 78 +++++++++++++++++++
    1 file changed, 78 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml

    diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml
    new file mode 100644
    index 000000000000..9c59a20a6032
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml
    @@ -0,0 +1,78 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: NXP IMX8QXP ADC bindings
    +
    +maintainers:
    + - Cai Huoqing <caihuoqing@baidu.com>
    +
    +description:
    + Supports the ADC found on the IMX8QXP SoC.
    +
    +properties:
    + compatible:
    + const: nxp,imx8qxp-adc
    +
    + reg:
    + maxItems: 1
    +
    + interrupts:
    + maxItems: 1
    +
    + clocks:
    + maxItems: 2
    +
    + clock-names:
    + items:
    + - const: per
    + - const: ipg
    +
    + assigned-clocks:
    + maxItems: 1
    +
    + assigned-clock-rates:
    + maxItems: 1
    +
    + power-domains:
    + maxItems: 1
    +
    + "#io-channel-cells":
    + const: 1
    +
    +required:
    + - compatible
    + - reg
    + - interrupts
    + - clocks
    + - clock-names
    + - assigned-clocks
    + - assigned-clock-rates
    + - power-domains
    + - "#io-channel-cells"
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    + #include <dt-bindings/firmware/imx/rsrc.h>
    + soc {
    + #address-cells = <2>;
    + #size-cells = <2>;
    + adc@5a880000 {
    + compatible = "nxp,imx8qxp-adc";
    + reg = <0x0 0x5a880000 0x0 0x10000>;
    + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&clk IMX_SC_R_ADC_0>,
    + <&clk IMX_SC_R_ADC_0>;
    + clock-names = "per", "ipg";
    + assigned-clocks = <&clk IMX_SC_R_ADC_0>;
    + assigned-clock-rates = <24000000>;
    + power-domains = <&pd IMX_SC_R_ADC_0>;
    + #io-channel-cells = <1>;
    + };
    + };
    +...
    --
    2.25.1
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