Messages in this thread | | | Subject | Re: [PATCH v2 2/2] clk: qcom: gcc-sdm660: Remove transient global "xo" clock | From | AngeloGioacchino Del Regno <> | Date | Thu, 2 Sep 2021 09:28:02 +0200 |
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Il 30/08/21 20:24, Marijn Suijten ha scritto: > The DSI PHY/PLL was relying on a global "xo" clock to be found, but the > real clock is named "xo_board" in the DT. The standard nowadays is to > never use global clock names anymore but require the firmware (DT) to > provide every clock binding explicitly with .fw_name. The DSI PLLs have > since been converted to this mechanism (specifically 14nm for SDM660) > and this transient clock can now be removed. > > This issue was originally discovered in: > https://lore.kernel.org/linux-arm-msm/386db1a6-a1cd-3c7d-a88e-dc83f8a1be96@somainline.org/ > and prevented the removal of "xo" at that time. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> --- > drivers/clk/qcom/gcc-sdm660.c | 14 -------------- > 1 file changed, 14 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c > index 9b97425008ce..16fd16351f95 100644 > --- a/drivers/clk/qcom/gcc-sdm660.c > +++ b/drivers/clk/qcom/gcc-sdm660.c > @@ -37,19 +37,6 @@ enum { > P_GPLL1_EARLY_DIV, > }; > > -static struct clk_fixed_factor xo = { > - .mult = 1, > - .div = 1, > - .hw.init = &(struct clk_init_data){ > - .name = "xo", > - .parent_data = &(const struct clk_parent_data) { > - .fw_name = "xo" > - }, > - .num_parents = 1, > - .ops = &clk_fixed_factor_ops, > - }, > -}; > - > static struct clk_alpha_pll gpll0_early = { > .offset = 0x0, > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > @@ -2281,7 +2268,6 @@ static struct gdsc pcie_0_gdsc = { > }; > > static struct clk_hw *gcc_sdm660_hws[] = { > - &xo.hw, > &gpll0_early_div.hw, > &gpll1_early_div.hw, > }; >
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