Messages in this thread | | | Subject | Re: [PATCH Part2 v5 01/45] x86/cpufeatures: Add SEV-SNP CPU feature | From | Brijesh Singh <> | Date | Thu, 16 Sep 2021 12:35:07 -0500 |
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On 9/16/21 11:56 AM, Borislav Petkov wrote: > On Fri, Aug 20, 2021 at 10:58:34AM -0500, Brijesh Singh wrote: >> Add CPU feature detection for Secure Encrypted Virtualization with >> Secure Nested Paging. This feature adds a strong memory integrity >> protection to help prevent malicious hypervisor-based attacks like >> data replay, memory re-mapping, and more. >> >> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kernel/cpu/amd.c | 3 ++- >> tools/arch/x86/include/asm/cpufeatures.h | 1 + >> 3 files changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >> index d0ce5cfd3ac1..62f458680772 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -398,6 +398,7 @@ >> #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ >> #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ >> #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ >> +#define X86_FEATURE_SEV_SNP (19*32+4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ > > s/AMD Secure Encrypted Virtualization/AMD SEV/g > > Bit 1 above already has that string - no need for repeating it > everywhere. > > Also, note the vertical alignment (space after the '+'): > > (19*32+ 4) >
Noted. I will fix in next rev. thanks
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