Messages in this thread | | | Date | Wed, 15 Sep 2021 10:35:17 +0530 | From | okukatla@codeauro ... | Subject | Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider |
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On 2021-09-04 00:36, Stephen Boyd wrote: > Quoting Odelu Kukatla (2021-08-20 04:23:41) >> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 53a21d0..cf59b47 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1848,6 +1848,17 @@ >> }; >> }; >> >> + epss_l3: interconnect@18590000 { >> + compatible = "qcom,sc7280-epss-l3"; >> + reg = <0 0x18590000 0 1000>, > > Is this supposed to be 0x1000? > No, This is 1000 or 0x3E8. >> + <0 0x18591000 0 0x100>, >> + <0 0x18592000 0 0x100>, >> + <0 0x18593000 0 0x100>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >> GCC_GPLL0>; >> + clock-names = "xo", "alternate"; >> + #interconnect-cells = <1>; >> + }; >> + >> cpufreq_hw: cpufreq@18591000 { >> compatible = "qcom,cpufreq-epss"; >> reg = <0 0x18591100 0 0x900>, >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >> Forum, >> a Linux Foundation Collaborative Project >>
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