Messages in this thread | | | Date | Fri, 10 Sep 2021 21:25:01 +0000 | From | Sean Christopherson <> | Subject | Re: [PATCH v4 1/6] x86/feat_ctl: Add new VMX feature, Tertiary VM-Execution control |
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x86/cpu: is probaby more appropriate, this touches more than just feat_ctl.
On Mon, Aug 09, 2021, Zeng Guang wrote: > From: Robert Hoo <robert.hu@linux.intel.com> > > New VMX capability MSR IA32_VMX_PROCBASED_CTLS3 conresponse to this new > VM-Execution control field. And it is 64bit allow-1 semantics, not like > previous capability MSRs 32bit allow-0 and 32bit allow-1. So with Tertiary > VM-Execution control field introduced, 2 vmx_feature leaves are introduced, > TERTIARY_CTLS_LOW and TERTIARY_CTLS_HIGH. > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> > Signed-off-by: Zeng Guang <guang.zeng@intel.com> > ---
Nits aside,
Reviewed-by: Sean Christopherson <seanjc@google.com>
> @@ -22,7 +24,7 @@ enum vmx_feature_leafs { > > static void init_vmx_capabilities(struct cpuinfo_x86 *c) > { > - u32 supported, funcs, ept, vpid, ign; > + u32 supported, funcs, ept, vpid, ign, low, high; > > BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS); > > @@ -42,6 +44,13 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) > rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported); > c->vmx_capability[SECONDARY_CTLS] = supported; > > + /* > + * For tertiary execution controls MSR, it's actually a 64bit allowed-1. > + */
Maybe something like this to better fit on one line?
/* All 64 bits of tertiary controls MSR are allowed-1 settings. */
> + rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high); > + c->vmx_capability[TERTIARY_CTLS_LOW] = low; > + c->vmx_capability[TERTIARY_CTLS_HIGH] = high; > + > rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported); > rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs); > > -- > 2.25.1 >
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