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    SubjectRe: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state
    On Fri, Aug 20, 2021 at 06:30:02PM +0000, Machnikowski, Maciej wrote:

    > So to be able to control SyncE we need 2 interfaces:
    > - Interface to enable the recovered clock output at the given pin
    > - interface to monitor the DPLL to see if the clock that we got is valid, or not.
    >
    > If it comes to ESMC (G.8264) messages, SyncE itself can run in 2 modes (slides 29/30 will give you more details):
    > - QL-Disabled - with no ESMC messages - it base on the local information from the PLL to make all decisions
    > - QL-Enabled - that adds ESMC and quality message transfer between the nodes.

    How do you get the QL codes from this?

    +enum if_eec_state {
    + IF_EEC_STATE_INVALID = 0,
    + IF_EEC_STATE_FREERUN,
    + IF_EEC_STATE_LOCKACQ,
    + IF_EEC_STATE_LOCKREC,
    + IF_EEC_STATE_LOCKED,
    + IF_EEC_STATE_HOLDOVER,
    + IF_EEC_STATE_OPEN_LOOP,
    + __IF_EEC_STATE_MAX,
    +};

    Thanks,
    Richard

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