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    SubjectRe: [PATCH v3 3/6] staging: r8188eu: add error handling of rtw_read8
    Hi Pavel,

    Thank you for the patch! Yet something to improve:

    [auto build test ERROR on staging/staging-testing]

    url: https://github.com/0day-ci/linux/commits/Pavel-Skripkin/staging-r8188eu-remove-read-write-_macreg/20210824-162756
    base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git 093991aaadf0fbb34184fa37a46e7a157da3f386
    config: x86_64-allyesconfig (attached as .config)
    compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
    reproduce (this is a W=1 build):
    # https://github.com/0day-ci/linux/commit/d4e4bbed4e59df37967086f60fe92cb1b4504d37
    git remote add linux-review https://github.com/0day-ci/linux
    git fetch --no-tags linux-review Pavel-Skripkin/staging-r8188eu-remove-read-write-_macreg/20210824-162756
    git checkout d4e4bbed4e59df37967086f60fe92cb1b4504d37
    # save the attached .config to linux build tree
    mkdir build_dir
    make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/staging/r8188eu/

    If you fix the issue, kindly add following tag as appropriate
    Reported-by: kernel test robot <lkp@intel.com>

    All errors (new ones prefixed by >>):

    drivers/staging/r8188eu/hal/usb_halinit.c: In function 'SetHwReg8188EU':
    >> drivers/staging/r8188eu/hal/usb_halinit.c:2022:3: error: a label can only be part of a statement and a declaration is not a statement
    2022 | u8 tmp;
    | ^~


    vim +2022 drivers/staging/r8188eu/hal/usb_halinit.c

    1450
    1451 static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
    1452 {
    1453 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
    1454 struct dm_priv *pdmpriv = &haldata->dmpriv;
    1455 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
    1456 int error;
    1457 u8 tmp;
    1458
    1459 switch (variable) {
    1460 case HW_VAR_MEDIA_STATUS:
    1461 {
    1462 u8 val8;
    1463
    1464 error = rtw_read8(Adapter, MSR, &val8);
    1465 if (error)
    1466 return;
    1467
    1468 val8 &= 0x0c;
    1469 val8 |= *((u8 *)val);
    1470 rtw_write8(Adapter, MSR, val8);
    1471 }
    1472 break;
    1473 case HW_VAR_MEDIA_STATUS1:
    1474 {
    1475 u8 val8;
    1476
    1477 error = rtw_read8(Adapter, MSR, &val8);
    1478 if (error)
    1479 return;
    1480
    1481 val8 &= 0x03;
    1482 val8 |= *((u8 *)val) << 2;
    1483 rtw_write8(Adapter, MSR, val8);
    1484 }
    1485 break;
    1486 case HW_VAR_SET_OPMODE:
    1487 hw_var_set_opmode(Adapter, variable, val);
    1488 break;
    1489 case HW_VAR_MAC_ADDR:
    1490 hw_var_set_macaddr(Adapter, variable, val);
    1491 break;
    1492 case HW_VAR_BSSID:
    1493 hw_var_set_bssid(Adapter, variable, val);
    1494 break;
    1495 case HW_VAR_BASIC_RATE:
    1496 {
    1497 u16 BrateCfg = 0;
    1498 u8 RateIndex = 0;
    1499
    1500 /* 2007.01.16, by Emily */
    1501 /* Select RRSR (in Legacy-OFDM and CCK) */
    1502 /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
    1503 /* We do not use other rates. */
    1504 HalSetBrateCfg(Adapter, val, &BrateCfg);
    1505 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
    1506
    1507 /* 2011.03.30 add by Luke Lee */
    1508 /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
    1509 /* because CCK 2M has poor TXEVM */
    1510 /* CCK 5.5M & 11M ACK should be enabled for better performance */
    1511
    1512 BrateCfg = (BrateCfg | 0xd) & 0x15d;
    1513 haldata->BasicRateSet = BrateCfg;
    1514
    1515 BrateCfg |= 0x01; /* default enable 1M ACK rate */
    1516 /* Set RRSR rate table. */
    1517 rtw_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
    1518 rtw_write8(Adapter, REG_RRSR + 1, (BrateCfg >> 8) & 0xff);
    1519
    1520 error = rtw_read8(Adapter, REG_RRSR + 2, &tmp);
    1521 if (error)
    1522 return;
    1523
    1524 rtw_write8(Adapter, REG_RRSR + 2, tmp & 0xf0);
    1525
    1526 /* Set RTS initial rate */
    1527 while (BrateCfg > 0x1) {
    1528 BrateCfg = (BrateCfg >> 1);
    1529 RateIndex++;
    1530 }
    1531 /* Ziv - Check */
    1532 rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
    1533 }
    1534 break;
    1535 case HW_VAR_TXPAUSE:
    1536 rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
    1537 break;
    1538 case HW_VAR_BCN_FUNC:
    1539 hw_var_set_bcn_func(Adapter, variable, val);
    1540 break;
    1541 case HW_VAR_CORRECT_TSF:
    1542 {
    1543 u64 tsf;
    1544 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
    1545 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
    1546
    1547 tsf = pmlmeext->TSFValue - do_div(pmlmeext->TSFValue,
    1548 pmlmeinfo->bcn_interval * 1024) - 1024; /* us */
    1549
    1550 if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
    1551 StopTxBeacon(Adapter);
    1552
    1553 /* disable related TSF function */
    1554 error = rtw_read8(Adapter, REG_BCN_CTRL, &tmp);
    1555 if (error)
    1556 return;
    1557
    1558 rtw_write8(Adapter, REG_BCN_CTRL, tmp & (~BIT(3)));
    1559
    1560 rtw_write32(Adapter, REG_TSFTR, tsf);
    1561 rtw_write32(Adapter, REG_TSFTR + 4, tsf >> 32);
    1562
    1563 /* enable related TSF function */
    1564 error = rtw_read8(Adapter, REG_BCN_CTRL, &tmp);
    1565 if (error)
    1566 return;
    1567
    1568 rtw_write8(Adapter, REG_BCN_CTRL, tmp | BIT(3));
    1569
    1570 if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
    1571 ResumeTxBeacon(Adapter);
    1572 }
    1573 break;
    1574 case HW_VAR_CHECK_BSSID:
    1575 if (*((u8 *)val)) {
    1576 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_DATA | RCR_CBSSID_BCN);
    1577 } else {
    1578 u32 val32;
    1579
    1580 val32 = rtw_read32(Adapter, REG_RCR);
    1581
    1582 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
    1583
    1584 rtw_write32(Adapter, REG_RCR, val32);
    1585 }
    1586 break;
    1587 case HW_VAR_MLME_DISCONNECT:
    1588 /* Set RCR to not to receive data frame when NO LINK state */
    1589 /* reject all data frames */
    1590 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
    1591
    1592 /* reset TSF */
    1593 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
    1594
    1595 /* disable update TSF */
    1596 error = rtw_read8(Adapter, REG_BCN_CTRL, &tmp);
    1597 if (error)
    1598 return;
    1599
    1600 rtw_write8(Adapter, REG_BCN_CTRL, tmp | BIT(4));
    1601 break;
    1602 case HW_VAR_MLME_SITESURVEY:
    1603 if (*((u8 *)val)) { /* under sitesurvey */
    1604 /* config RCR to receive different BSSID & not to receive data frame */
    1605 u32 v = rtw_read32(Adapter, REG_RCR);
    1606
    1607 v &= ~(RCR_CBSSID_BCN);
    1608 rtw_write32(Adapter, REG_RCR, v);
    1609 /* reject all data frame */
    1610 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
    1611
    1612 /* disable update TSF */
    1613 error = rtw_read8(Adapter, REG_BCN_CTRL, &tmp);
    1614 if (error)
    1615 return;
    1616 rtw_write8(Adapter, REG_BCN_CTRL, tmp | BIT(4));
    1617 } else { /* sitesurvey done */
    1618 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
    1619 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
    1620
    1621 error = rtw_read8(Adapter, REG_BCN_CTRL, &tmp);
    1622 if (error)
    1623 return;
    1624
    1625 if ((is_client_associated_to_ap(Adapter)) ||
    1626 ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
    1627 /* enable to rx data frame */
    1628 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
    1629
    1630 /* enable update TSF */
    1631 rtw_write8(Adapter, REG_BCN_CTRL, tmp & (~BIT(4)));
    1632 } else if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
    1633 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
    1634 /* enable update TSF */
    1635 rtw_write8(Adapter, REG_BCN_CTRL, tmp & (~BIT(4)));
    1636 }
    1637
    1638 if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
    1639 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_BCN);
    1640 } else {
    1641 if (Adapter->in_cta_test) {
    1642 u32 v = rtw_read32(Adapter, REG_RCR);
    1643 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
    1644 rtw_write32(Adapter, REG_RCR, v);
    1645 } else {
    1646 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_BCN);
    1647 }
    1648 }
    1649 }
    1650 break;
    1651 case HW_VAR_MLME_JOIN:
    1652 {
    1653 u8 RetryLimit = 0x30;
    1654 u8 type = *((u8 *)val);
    1655 u8 tmp;
    1656 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
    1657
    1658 if (type == 0) { /* prepare to join */
    1659 /* enable to rx data frame.Accept all data frame */
    1660 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
    1661
    1662 if (Adapter->in_cta_test) {
    1663 u32 v = rtw_read32(Adapter, REG_RCR);
    1664 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
    1665 rtw_write32(Adapter, REG_RCR, v);
    1666 } else {
    1667 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_DATA | RCR_CBSSID_BCN);
    1668 }
    1669
    1670 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
    1671 RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
    1672 else /* Ad-hoc Mode */
    1673 RetryLimit = 0x7;
    1674 } else if (type == 1) {
    1675 /* joinbss_event call back when join res < 0 */
    1676 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
    1677 } else if (type == 2) {
    1678 /* sta add event call back */
    1679 /* enable update TSF */
    1680 error = rtw_read8(Adapter, REG_BCN_CTRL, &tmp);
    1681 if (error)
    1682 return;
    1683
    1684 rtw_write8(Adapter, REG_BCN_CTRL, tmp & (~BIT(4)));
    1685
    1686 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
    1687 RetryLimit = 0x7;
    1688 }
    1689 rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
    1690 }
    1691 break;
    1692 case HW_VAR_BEACON_INTERVAL:
    1693 rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
    1694 break;
    1695 case HW_VAR_SLOT_TIME:
    1696 {
    1697 u8 u1bAIFS, aSifsTime;
    1698 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
    1699 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
    1700
    1701 rtw_write8(Adapter, REG_SLOT, val[0]);
    1702
    1703 if (pmlmeinfo->WMM_enable == 0) {
    1704 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
    1705 aSifsTime = 10;
    1706 else
    1707 aSifsTime = 16;
    1708
    1709 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
    1710
    1711 /* <Roger_EXP> Temporary removed, 2008.06.20. */
    1712 rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
    1713 rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
    1714 rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
    1715 rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
    1716 }
    1717 }
    1718 break;
    1719 case HW_VAR_RESP_SIFS:
    1720 /* RESP_SIFS for CCK */
    1721 rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /* SIFS_T2T_CCK (0x08) */
    1722 rtw_write8(Adapter, REG_R2T_SIFS + 1, val[1]); /* SIFS_R2T_CCK(0x08) */
    1723 /* RESP_SIFS for OFDM */
    1724 rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
    1725 rtw_write8(Adapter, REG_T2T_SIFS + 1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
    1726 break;
    1727 case HW_VAR_ACK_PREAMBLE:
    1728 {
    1729 u8 regTmp;
    1730 u8 bShortPreamble = *((bool *)val);
    1731 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
    1732 regTmp = (haldata->nCur40MhzPrimeSC) << 5;
    1733 if (bShortPreamble)
    1734 regTmp |= 0x80;
    1735
    1736 rtw_write8(Adapter, REG_RRSR + 2, regTmp);
    1737 }
    1738 break;
    1739 case HW_VAR_SEC_CFG:
    1740 rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
    1741 break;
    1742 case HW_VAR_DM_FLAG:
    1743 podmpriv->SupportAbility = *((u8 *)val);
    1744 break;
    1745 case HW_VAR_DM_FUNC_OP:
    1746 if (val[0])
    1747 podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
    1748 else
    1749 podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
    1750 break;
    1751 case HW_VAR_DM_FUNC_SET:
    1752 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
    1753 pdmpriv->DMFlag = pdmpriv->InitDMFlag;
    1754 podmpriv->SupportAbility = pdmpriv->InitODMFlag;
    1755 } else {
    1756 podmpriv->SupportAbility |= *((u32 *)val);
    1757 }
    1758 break;
    1759 case HW_VAR_DM_FUNC_CLR:
    1760 podmpriv->SupportAbility &= *((u32 *)val);
    1761 break;
    1762 case HW_VAR_CAM_EMPTY_ENTRY:
    1763 {
    1764 u8 ucIndex = *((u8 *)val);
    1765 u8 i;
    1766 u32 ulCommand = 0;
    1767 u32 ulContent = 0;
    1768 u32 ulEncAlgo = CAM_AES;
    1769
    1770 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
    1771 /* filled id in CAM config 2 byte */
    1772 if (i == 0)
    1773 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);
    1774 else
    1775 ulContent = 0;
    1776 /* polling bit, and No Write enable, and address */
    1777 ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
    1778 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
    1779 /* write content 0 is equall to mark invalid */
    1780 rtw_write32(Adapter, WCAMI, ulContent); /* delay_ms(40); */
    1781 rtw_write32(Adapter, RWCAM, ulCommand); /* delay_ms(40); */
    1782 }
    1783 }
    1784 break;
    1785 case HW_VAR_CAM_INVALID_ALL:
    1786 rtw_write32(Adapter, RWCAM, BIT(31) | BIT(30));
    1787 break;
    1788 case HW_VAR_CAM_WRITE:
    1789 {
    1790 u32 cmd;
    1791 u32 *cam_val = (u32 *)val;
    1792 rtw_write32(Adapter, WCAMI, cam_val[0]);
    1793
    1794 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
    1795 rtw_write32(Adapter, RWCAM, cmd);
    1796 }
    1797 break;
    1798 case HW_VAR_AC_PARAM_VO:
    1799 rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
    1800 break;
    1801 case HW_VAR_AC_PARAM_VI:
    1802 rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
    1803 break;
    1804 case HW_VAR_AC_PARAM_BE:
    1805 haldata->AcParam_BE = ((u32 *)(val))[0];
    1806 rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
    1807 break;
    1808 case HW_VAR_AC_PARAM_BK:
    1809 rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
    1810 break;
    1811 case HW_VAR_ACM_CTRL:
    1812 {
    1813 u8 acm_ctrl = *((u8 *)val);
    1814 u8 AcmCtrl;
    1815
    1816 error = rtw_read8(Adapter, REG_ACMHWCTRL, &AcmCtrl);
    1817 if (error)
    1818 return;
    1819
    1820 if (acm_ctrl > 1)
    1821 AcmCtrl = AcmCtrl | 0x1;
    1822
    1823 if (acm_ctrl & BIT(3))
    1824 AcmCtrl |= AcmHw_VoqEn;
    1825 else
    1826 AcmCtrl &= (~AcmHw_VoqEn);
    1827
    1828 if (acm_ctrl & BIT(2))
    1829 AcmCtrl |= AcmHw_ViqEn;
    1830 else
    1831 AcmCtrl &= (~AcmHw_ViqEn);
    1832
    1833 if (acm_ctrl & BIT(1))
    1834 AcmCtrl |= AcmHw_BeqEn;
    1835 else
    1836 AcmCtrl &= (~AcmHw_BeqEn);
    1837
    1838 DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
    1839 rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
    1840 }
    1841 break;
    1842 case HW_VAR_AMPDU_MIN_SPACE:
    1843 {
    1844 u8 MinSpacingToSet;
    1845 u8 SecMinSpace;
    1846 u8 tmp;
    1847
    1848 MinSpacingToSet = *((u8 *)val);
    1849 if (MinSpacingToSet <= 7) {
    1850 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
    1851 case _NO_PRIVACY_:
    1852 case _AES_:
    1853 SecMinSpace = 0;
    1854 break;
    1855 case _WEP40_:
    1856 case _WEP104_:
    1857 case _TKIP_:
    1858 case _TKIP_WTMIC_:
    1859 SecMinSpace = 6;
    1860 break;
    1861 default:
    1862 SecMinSpace = 7;
    1863 break;
    1864 }
    1865 if (MinSpacingToSet < SecMinSpace)
    1866 MinSpacingToSet = SecMinSpace;
    1867
    1868 error = rtw_read8(Adapter, REG_AMPDU_MIN_SPACE, &tmp);
    1869 if (error)
    1870 return;
    1871
    1872 rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (tmp & 0xf8) |
    1873 MinSpacingToSet);
    1874 }
    1875 }
    1876 break;
    1877 case HW_VAR_AMPDU_FACTOR:
    1878 {
    1879 u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
    1880 u8 FactorToSet;
    1881 u8 *pRegToSet;
    1882 u8 index = 0;
    1883
    1884 pRegToSet = RegToSet_Normal; /* 0xb972a841; */
    1885 FactorToSet = *((u8 *)val);
    1886 if (FactorToSet <= 3) {
    1887 FactorToSet = (1 << (FactorToSet + 2));
    1888 if (FactorToSet > 0xf)
    1889 FactorToSet = 0xf;
    1890
    1891 for (index = 0; index < 4; index++) {
    1892 if ((pRegToSet[index] & 0xf0) > (FactorToSet << 4))
    1893 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet << 4);
    1894
    1895 if ((pRegToSet[index] & 0x0f) > FactorToSet)
    1896 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
    1897
    1898 rtw_write8(Adapter, (REG_AGGLEN_LMT + index), pRegToSet[index]);
    1899 }
    1900 }
    1901 }
    1902 break;
    1903 case HW_VAR_RXDMA_AGG_PG_TH:
    1904 {
    1905 u8 threshold = *((u8 *)val);
    1906 if (threshold == 0)
    1907 threshold = haldata->UsbRxAggPageCount;
    1908 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
    1909 }
    1910 break;
    1911 case HW_VAR_SET_RPWM:
    1912 break;
    1913 case HW_VAR_H2C_FW_PWRMODE:
    1914 {
    1915 u8 psmode = (*(u8 *)val);
    1916
    1917 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
    1918 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
    1919 if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
    1920 ODM_RF_Saving(podmpriv, true);
    1921 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
    1922 }
    1923 break;
    1924 case HW_VAR_H2C_FW_JOINBSSRPT:
    1925 {
    1926 u8 mstatus = (*(u8 *)val);
    1927 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
    1928 }
    1929 break;
    1930 #ifdef CONFIG_88EU_P2P
    1931 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
    1932 {
    1933 u8 p2p_ps_state = (*(u8 *)val);
    1934 rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
    1935 }
    1936 break;
    1937 #endif
    1938 case HW_VAR_INITIAL_GAIN:
    1939 {
    1940 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
    1941 u32 rx_gain = ((u32 *)(val))[0];
    1942
    1943 if (rx_gain == 0xff) {/* restore rx gain */
    1944 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
    1945 } else {
    1946 pDigTable->BackupIGValue = pDigTable->CurIGValue;
    1947 ODM_Write_DIG(podmpriv, rx_gain);
    1948 }
    1949 }
    1950 break;
    1951 case HW_VAR_TRIGGER_GPIO_0:
    1952 rtl8192cu_trigger_gpio_0(Adapter);
    1953 break;
    1954 case HW_VAR_RPT_TIMER_SETTING:
    1955 {
    1956 u16 min_rpt_time = (*(u16 *)val);
    1957 ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
    1958 }
    1959 break;
    1960 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
    1961 {
    1962 u8 Optimum_antenna = (*(u8 *)val);
    1963 u8 Ant;
    1964 /* switch antenna to Optimum_antenna */
    1965 if (haldata->CurAntenna != Optimum_antenna) {
    1966 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
    1967 ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant);
    1968
    1969 haldata->CurAntenna = Optimum_antenna;
    1970 }
    1971 }
    1972 break;
    1973 case HW_VAR_EFUSE_BYTES: /* To set EFUE total used bytes, added by Roger, 2008.12.22. */
    1974 haldata->EfuseUsedBytes = *((u16 *)val);
    1975 break;
    1976 case HW_VAR_FIFO_CLEARN_UP:
    1977 {
    1978 struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
    1979 u8 trycnt = 100;
    1980
    1981 /* pause tx */
    1982 rtw_write8(Adapter, REG_TXPAUSE, 0xff);
    1983
    1984 /* keep sn */
    1985 Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter, REG_NQOS_SEQ);
    1986
    1987 if (!pwrpriv->bkeepfwalive) {
    1988 /* RX DMA stop */
    1989 rtw_write32(Adapter, REG_RXPKT_NUM, (rtw_read32(Adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
    1990 do {
    1991 if (!(rtw_read32(Adapter, REG_RXPKT_NUM) & RXDMA_IDLE))
    1992 break;
    1993 } while (trycnt--);
    1994 if (trycnt == 0)
    1995 DBG_88E("Stop RX DMA failed......\n");
    1996
    1997 /* RQPN Load 0 */
    1998 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0);
    1999 rtw_write32(Adapter, REG_RQPN, 0x80000000);
    2000 mdelay(10);
    2001 }
    2002 }
    2003 break;
    2004 case HW_VAR_CHECK_TXBUF:
    2005 break;
    2006 case HW_VAR_APFM_ON_MAC:
    2007 haldata->bMacPwrCtrlOn = *val;
    2008 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
    2009 break;
    2010 case HW_VAR_TX_RPT_MAX_MACID:
    2011 {
    2012 u8 maxMacid = *val;
    2013 DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid + 1);
    2014 rtw_write8(Adapter, REG_TX_RPT_CTRL + 1, maxMacid + 1);
    2015 }
    2016 break;
    2017 case HW_VAR_H2C_MEDIA_STATUS_RPT:
    2018 rtl8188e_set_FwMediaStatus_cmd(Adapter, (*(__le16 *)val));
    2019 break;
    2020 case HW_VAR_BCN_VALID:
    2021 /* BCN_VALID, BIT(16) of REG_TDECTRL = BIT(0) of REG_TDECTRL+2, write 1 to clear, Clear by sw */
    > 2022 u8 tmp;
    2023
    2024 error = rtw_read8(Adapter, REG_TDECTRL + 2, &tmp);
    2025 if (error)
    2026 return;
    2027
    2028 rtw_write8(Adapter, REG_TDECTRL + 2, tmp | BIT(0));
    2029 break;
    2030 default:
    2031 break;
    2032 }
    2033

    ---
    0-DAY CI Kernel Test Service, Intel Corporation
    https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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