Messages in this thread | | | Date | Thu, 19 Aug 2021 10:47:59 +0200 | From | Sebastian Andrzej Siewior <> | Subject | Re: [PATCH v2] usb: chipidea: local_irq_save/restore added for hw_ep_prime |
| |
On 2021-08-19 08:50:27 [+0900], Jeaho Hwang wrote: > Without RT, udc_irq runs as a forced threaded irq handler, so it runs > without any interruption or preemption. NO similar case is found on > non-RT.
I see only a devm_request_irq() so no force-threading here. Booting with threadirqs would not lead to the problem since commit 81e2073c175b8 ("genirq: Disable interrupts for force threaded handlers")
… > > If this function here is sensitive to timing (say the cpu_relax() loop > > gets interrupt for 1ms) then it has to be documented as such. > > The controller sets ENDPTSETUPSTAT register if the host sent a setup packet. > yes it is a timing problem. I will document that and resubmit again if > you agree that local_irq_save could help from the timing problem. > > Thanks for the advice.
If it is really a timing issue in the function as you describe below then disabling interrupts would help and it is indeed an RT only issue.
So you read OP_ENDPTSETUPSTAT, it is 0, all good. You write OP_ENDPTPRIME, wait for it to be cleared. Then you read OP_ENDPTSETUPSTAT again and if it is 0, all good.
And the TWD interrupt could delay say the second read would read 1 and it is invalidated. Which looks odd. However, it is "okay" if the TWD interrupt happens after the second read? Even if the host sends a setup packet, nothing breaks? Do you have numbers on how long irq-off section is here? It seems to depend on how long the HW needs to clear the OP_ENDPTPRIME bits.
Sebastian
| |