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SubjectRe: [PATCH v2 2/2] pinctrl: Add Intel Keem Bay pinctrl driver
Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on pinctrl/devel]
[also build test WARNING on linux/master linus/master v5.13 next-20210709]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/lakshmi-sowjanya-d-intel-com/Add-pinctrl-support-for-Intel-Keem-Bay-SoC/20210709-143204
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/42983046a7b0389b36687ab5ab77d97749127fc7
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review lakshmi-sowjanya-d-intel-com/Add-pinctrl-support-for-Intel-Keem-Bay-SoC/20210709-143204
git checkout 42983046a7b0389b36687ab5ab77d97749127fc7
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_gpio_irq_handler':
>> drivers/pinctrl/pinctrl-keembay.c:1244:20: warning: variable 'trig' set but not used [-Wunused-but-set-variable]
1244 | unsigned int src, trig, pin, val;
| ^~~~


vim +/trig +1244 drivers/pinctrl/pinctrl-keembay.c

1238
1239 static void keembay_gpio_irq_handler(struct irq_desc *desc)
1240 {
1241 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1242 unsigned int kmb_irq = irq_desc_get_irq(desc);
1243 unsigned long reg, clump = 0, bit = 0;
> 1244 unsigned int src, trig, pin, val;
1245 struct irq_chip *parent_chip;
1246 struct keembay_pinctrl *kpc;
1247
1248 /* Identify GPIO interrupt number from GIC interrupt number */
1249 for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
1250 if (kmb_irq == gc->irq.parents[src])
1251 break;
1252 }
1253
1254 if (src == KEEMBAY_GPIO_NUM_IRQ)
1255 return;
1256
1257 parent_chip = irq_desc_get_chip(desc);
1258 kpc = gpiochip_get_data(gc);
1259
1260 chained_irq_enter(parent_chip, desc);
1261 reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1262 trig = kpc->irq[src].trigger;
1263
1264 /*
1265 * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit
1266 * and input values were checked to identify the source of the
1267 * Interrupt. The checked enable bit positions are 7, 15, 23 and 31.
1268 */
1269 for_each_set_clump8(bit, clump, &reg, BITS_PER_TYPE(typeof(reg))) {
1270 pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE;
1271 val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
1272 kmb_irq = irq_linear_revmap(gc->irq.domain, pin);
1273
1274 /* Checks if the interrupt is enabled */
1275 if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE))
1276 generic_handle_irq(kmb_irq);
1277 }
1278 chained_irq_exit(parent_chip, desc);
1279 }
1280

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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