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    Subject[PATCH v5 12/13] KVM: x86/vmx: Check Arch LBR config when return perf capabilities
    Date
    Two new bit fields(VM_EXIT_CLEAR_IA32_LBR_CTL, VM_ENTRY_LOAD_IA32_LBR_CTL)
    are added to support guest Arch LBR. These two bits should be set in order
    to make Arch LBR workable in both guest and host.

    Co-developed-by: Like Xu <like.xu@linux.intel.com>
    Signed-off-by: Like Xu <like.xu@linux.intel.com>
    Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
    ---
    arch/x86/include/asm/vmx.h | 2 ++
    arch/x86/kvm/vmx/capabilities.h | 25 +++++++++++++++++--------
    arch/x86/kvm/vmx/vmx.c | 6 ++++--
    3 files changed, 23 insertions(+), 10 deletions(-)

    diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
    index ea3be961cc8e..d9b1dffc4638 100644
    --- a/arch/x86/include/asm/vmx.h
    +++ b/arch/x86/include/asm/vmx.h
    @@ -95,6 +95,7 @@
    #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
    #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
    #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
    +#define VM_EXIT_CLEAR_IA32_LBR_CTL 0x04000000

    #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff

    @@ -108,6 +109,7 @@
    #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
    #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
    #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
    +#define VM_ENTRY_LOAD_IA32_LBR_CTL 0x00200000

    #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff

    diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
    index aa0e7872fcc9..b65e4087c9a9 100644
    --- a/arch/x86/kvm/vmx/capabilities.h
    +++ b/arch/x86/kvm/vmx/capabilities.h
    @@ -377,20 +377,29 @@ static inline bool vmx_pt_mode_is_host_guest(void)
    return pt_mode == PT_MODE_HOST_GUEST;
    }

    -static inline u64 vmx_get_perf_capabilities(void)
    +static inline bool cpu_has_vmx_arch_lbr(void)
    {
    - u64 perf_cap = 0;
    -
    - if (boot_cpu_has(X86_FEATURE_PDCM))
    - rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap);
    -
    - perf_cap &= PMU_CAP_LBR_FMT;
    + return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_IA32_LBR_CTL) &&
    + (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_LBR_CTL);
    +}

    +static inline u64 vmx_get_perf_capabilities(void)
    +{
    /*
    * Since counters are virtualized, KVM would support full
    * width counting unconditionally, even if the host lacks it.
    */
    - return PMU_CAP_FW_WRITES | perf_cap;
    + u64 perf_cap = PMU_CAP_FW_WRITES;
    + u64 host_perf_cap = 0;
    +
    + if (boot_cpu_has(X86_FEATURE_PDCM))
    + rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap);
    +
    + perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT;
    + if (boot_cpu_has(X86_FEATURE_ARCH_LBR) && !cpu_has_vmx_arch_lbr())
    + perf_cap &= ~PMU_CAP_LBR_FMT;
    +
    + return perf_cap;
    }

    static inline u64 vmx_supported_debugctl(void)
    diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
    index 3eccda710495..ae12fd7ac44e 100644
    --- a/arch/x86/kvm/vmx/vmx.c
    +++ b/arch/x86/kvm/vmx/vmx.c
    @@ -2620,7 +2620,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
    VM_EXIT_LOAD_IA32_EFER |
    VM_EXIT_CLEAR_BNDCFGS |
    VM_EXIT_PT_CONCEAL_PIP |
    - VM_EXIT_CLEAR_IA32_RTIT_CTL;
    + VM_EXIT_CLEAR_IA32_RTIT_CTL |
    + VM_EXIT_CLEAR_IA32_LBR_CTL;
    if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
    &_vmexit_control) < 0)
    return -EIO;
    @@ -2644,7 +2645,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
    VM_ENTRY_LOAD_IA32_EFER |
    VM_ENTRY_LOAD_BNDCFGS |
    VM_ENTRY_PT_CONCEAL_PIP |
    - VM_ENTRY_LOAD_IA32_RTIT_CTL;
    + VM_ENTRY_LOAD_IA32_RTIT_CTL |
    + VM_ENTRY_LOAD_IA32_LBR_CTL;
    if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
    &_vmentry_control) < 0)
    return -EIO;
    --
    2.21.1
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