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    Subject[v12 09/20] clk: mediatek: Add MT8192 audio clock support
    Date
    Add MT8192 audio clock provider

    Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
    Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    ---
    drivers/clk/mediatek/Kconfig | 6 ++
    drivers/clk/mediatek/Makefile | 1 +
    drivers/clk/mediatek/clk-mt8192-aud.c | 118 ++++++++++++++++++++++++++
    3 files changed, 125 insertions(+)
    create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c

    diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
    index 6075b48377d5..909f423d7c4c 100644
    --- a/drivers/clk/mediatek/Kconfig
    +++ b/drivers/clk/mediatek/Kconfig
    @@ -508,6 +508,12 @@ config COMMON_CLK_MT8192
    help
    This driver supports MediaTek MT8192 basic clocks.

    +config COMMON_CLK_MT8192_AUDSYS
    + bool "Clock driver for MediaTek MT8192 audsys"
    + depends on COMMON_CLK_MT8192
    + help
    + This driver supports MediaTek MT8192 audsys clocks.
    +
    config COMMON_CLK_MT8516
    bool "Clock driver for MediaTek MT8516"
    depends on ARCH_MEDIATEK || COMPILE_TEST
    diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
    index fcde42160720..1d0f2e8e9661 100644
    --- a/drivers/clk/mediatek/Makefile
    +++ b/drivers/clk/mediatek/Makefile
    @@ -68,5 +68,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
    obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
    obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
    obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
    +obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
    obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
    obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
    diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c
    new file mode 100644
    index 000000000000..f28d56628045
    --- /dev/null
    +++ b/drivers/clk/mediatek/clk-mt8192-aud.c
    @@ -0,0 +1,118 @@
    +// SPDX-License-Identifier: GPL-2.0-only
    +//
    +// Copyright (c) 2021 MediaTek Inc.
    +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    +
    +#include <linux/clk-provider.h>
    +#include <linux/of_platform.h>
    +#include <linux/platform_device.h>
    +
    +#include "clk-mtk.h"
    +#include "clk-gate.h"
    +
    +#include <dt-bindings/clock/mt8192-clk.h>
    +
    +static const struct mtk_gate_regs aud0_cg_regs = {
    + .set_ofs = 0x0,
    + .clr_ofs = 0x0,
    + .sta_ofs = 0x0,
    +};
    +
    +static const struct mtk_gate_regs aud1_cg_regs = {
    + .set_ofs = 0x4,
    + .clr_ofs = 0x4,
    + .sta_ofs = 0x4,
    +};
    +
    +static const struct mtk_gate_regs aud2_cg_regs = {
    + .set_ofs = 0x8,
    + .clr_ofs = 0x8,
    + .sta_ofs = 0x8,
    +};
    +
    +#define GATE_AUD0(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
    +
    +#define GATE_AUD1(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
    +
    +#define GATE_AUD2(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
    +
    +static const struct mtk_gate aud_clks[] = {
    + /* AUD0 */
    + GATE_AUD0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
    + GATE_AUD0(CLK_AUD_22M, "aud_22m", "aud_engen1_sel", 8),
    + GATE_AUD0(CLK_AUD_24M, "aud_24m", "aud_engen2_sel", 9),
    + GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_engen2_sel", 18),
    + GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_engen1_sel", 19),
    + GATE_AUD0(CLK_AUD_TDM, "aud_tdm", "aud_1_sel", 20),
    + GATE_AUD0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
    + GATE_AUD0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
    + GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26),
    + GATE_AUD0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
    + GATE_AUD0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
    + /* AUD1 */
    + GATE_AUD1(CLK_AUD_I2S1_B, "aud_i2s1_b", "audio_sel", 4),
    + GATE_AUD1(CLK_AUD_I2S2_B, "aud_i2s2_b", "audio_sel", 5),
    + GATE_AUD1(CLK_AUD_I2S3_B, "aud_i2s3_b", "audio_sel", 6),
    + GATE_AUD1(CLK_AUD_I2S4_B, "aud_i2s4_b", "audio_sel", 7),
    + GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "audio_sel", 12),
    + GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "audio_sel", 13),
    + GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "audio_sel", 14),
    + GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 15),
    + GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 16),
    + GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel", 17),
    + GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "audio_sel", 20),
    + GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 21),
    + GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel", 28),
    + GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel", 29),
    + GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel", 30),
    + GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel", 31),
    + /* AUD2 */
    + GATE_AUD2(CLK_AUD_I2S5_B, "aud_i2s5_b", "audio_sel", 0),
    + GATE_AUD2(CLK_AUD_I2S6_B, "aud_i2s6_b", "audio_sel", 1),
    + GATE_AUD2(CLK_AUD_I2S7_B, "aud_i2s7_b", "audio_sel", 2),
    + GATE_AUD2(CLK_AUD_I2S8_B, "aud_i2s8_b", "audio_sel", 3),
    + GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4),
    +};
    +
    +static int clk_mt8192_aud_probe(struct platform_device *pdev)
    +{
    + struct clk_onecell_data *clk_data;
    + struct device_node *node = pdev->dev.of_node;
    + int r;
    +
    + clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
    + if (!clk_data)
    + return -ENOMEM;
    +
    + r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
    + if (r)
    + return r;
    +
    + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
    + if (r)
    + return r;
    +
    + r = devm_of_platform_populate(&pdev->dev);
    + if (r)
    + of_clk_del_provider(node);
    +
    + return r;
    +}
    +
    +static const struct of_device_id of_match_clk_mt8192_aud[] = {
    + { .compatible = "mediatek,mt8192-audsys", },
    + {}
    +};
    +
    +static struct platform_driver clk_mt8192_aud_drv = {
    + .probe = clk_mt8192_aud_probe,
    + .driver = {
    + .name = "clk-mt8192-aud",
    + .of_match_table = of_match_clk_mt8192_aud,
    + },
    +};
    +
    +builtin_platform_driver(clk_mt8192_aud_drv);
    --
    2.18.0
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      Last update: 2021-07-05 05:42    [W:3.334 / U:0.636 seconds]
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