Messages in this thread Patch in this message | | | From | Guangbin Huang <> | Subject | [PATCH net-next 1/4] arm64: barrier: add DGH macros to control memory accesses merging | Date | Fri, 30 Jul 2021 11:14:21 +0800 |
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From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
DGH prohibits merging memory accesses with Normal-NC or Device-GRE attributes before the hint instruction with any memory accesses appearing after the hint instruction. Provide macros to expose it to the arch code.
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by: Cheng Jian <cj.chengjian@huawei.com> Signed-off-by: Yufeng Mo <moyufeng@huawei.com> --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/include/asm/barrier.h | 1 + 2 files changed, 8 insertions(+)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 89faca0e740d..5a3348b5e9f3 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -90,6 +90,13 @@ .endm /* + * Data gathering hint + */ + .macro dgh + hint #6 + .endm + +/* * RAS Error Synchronization barrier */ .macro esb diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 451e11e5fd23..02e1735706d2 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -22,6 +22,7 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define dgh() asm volatile("hint #6" : : : "memory") #define psb_csync() asm volatile("hint #17" : : : "memory") #define tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") -- 2.8.1
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