Messages in this thread | | | Date | Tue, 27 Jul 2021 09:17:26 +0200 | From | Michael Walle <> | Subject | Re: [PATCH 2/2] mtd: spi-nor: micron-st: add support for mt25ql01g and mt25qu01g |
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Am 2021-07-23 13:27, schrieb Matthias Schiffer: > Split these mt25q models from the older n25q models by matching their > extended IDs to allow adding support for 4byte opcodes.
You will have to supply SFDP data for all these chips, please have a look at [1] how to do that.
Also, we'll switch to SFDP parsing, have a look at [2].
> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> > --- > drivers/mtd/spi-nor/micron-st.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/mtd/spi-nor/micron-st.c > b/drivers/mtd/spi-nor/micron-st.c > index d5baa8762c8d..2fca5de2504f 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -172,11 +172,17 @@ static const struct flash_info st_parts[] = { > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | > SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, > + { "mt25ql01g", INFO6(0x20ba21, 0x104400, 64 * 1024, 2048, > + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
As mentioned in my other mail, I don't see this chip supporting 0xc7 (BULK ERASE). Is erasing the whole chip working?
Thanks, -michael
> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | > SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6 | > NO_CHIP_ERASE) }, > + { "mt25qu01g", INFO6(0x20bb21, 0x104400, 64 * 1024, 2048, > + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | > NO_CHIP_ERASE) },
[1] https://lore.kernel.org/linux-mtd/7038f037de3e224016d269324517400d@walle.cc/ [2] https://lore.kernel.org/linux-mtd/20210727045222.905056-36-tudor.ambarus@microchip.com/
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