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    Subject[v14 20/21] clk: mediatek: Add MT8192 vdecsys clock support
    Date
    Add MT8192 vdecsys and vdecsys soc clock providers

    Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
    Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    ---
    drivers/clk/mediatek/Kconfig | 6 ++
    drivers/clk/mediatek/Makefile | 1 +
    drivers/clk/mediatek/clk-mt8192-vdec.c | 94 ++++++++++++++++++++++++++
    3 files changed, 101 insertions(+)
    create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c

    diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
    index eb4aa29d8106..31779f2c5c83 100644
    --- a/drivers/clk/mediatek/Kconfig
    +++ b/drivers/clk/mediatek/Kconfig
    @@ -568,6 +568,12 @@ config COMMON_CLK_MT8192_SCP_ADSP
    help
    This driver supports MediaTek MT8192 scp_adsp clocks.

    +config COMMON_CLK_MT8192_VDECSYS
    + bool "Clock driver for MediaTek MT8192 vdecsys"
    + depends on COMMON_CLK_MT8192
    + help
    + This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks.
    +
    config COMMON_CLK_MT8516
    bool "Clock driver for MediaTek MT8516"
    depends on ARCH_MEDIATEK || COMPILE_TEST
    diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
    index a336fe753e9a..887dd6bcf7f2 100644
    --- a/drivers/clk/mediatek/Makefile
    +++ b/drivers/clk/mediatek/Makefile
    @@ -78,5 +78,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o
    obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o
    obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
    obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
    +obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
    obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
    obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
    diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c
    new file mode 100644
    index 000000000000..b1d95cfbf22a
    --- /dev/null
    +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c
    @@ -0,0 +1,94 @@
    +// SPDX-License-Identifier: GPL-2.0-only
    +//
    +// Copyright (c) 2021 MediaTek Inc.
    +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    +
    +#include <linux/clk-provider.h>
    +#include <linux/of_device.h>
    +#include <linux/platform_device.h>
    +
    +#include "clk-mtk.h"
    +#include "clk-gate.h"
    +
    +#include <dt-bindings/clock/mt8192-clk.h>
    +
    +static const struct mtk_gate_regs vdec0_cg_regs = {
    + .set_ofs = 0x0,
    + .clr_ofs = 0x4,
    + .sta_ofs = 0x0,
    +};
    +
    +static const struct mtk_gate_regs vdec1_cg_regs = {
    + .set_ofs = 0x200,
    + .clr_ofs = 0x204,
    + .sta_ofs = 0x200,
    +};
    +
    +static const struct mtk_gate_regs vdec2_cg_regs = {
    + .set_ofs = 0x8,
    + .clr_ofs = 0xc,
    + .sta_ofs = 0x8,
    +};
    +
    +#define GATE_VDEC0(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
    +
    +#define GATE_VDEC1(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
    +
    +#define GATE_VDEC2(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
    +
    +static const struct mtk_gate vdec_clks[] = {
    + /* VDEC0 */
    + GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
    + GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
    + /* VDEC1 */
    + GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
    + GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
    + /* VDEC2 */
    + GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
    +};
    +
    +static const struct mtk_gate vdec_soc_clks[] = {
    + /* VDEC_SOC0 */
    + GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
    + GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
    + /* VDEC_SOC1 */
    + GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
    + GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
    + /* VDEC_SOC2 */
    + GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
    +};
    +
    +static const struct mtk_clk_desc vdec_desc = {
    + .clks = vdec_clks,
    + .num_clks = ARRAY_SIZE(vdec_clks),
    +};
    +
    +static const struct mtk_clk_desc vdec_soc_desc = {
    + .clks = vdec_soc_clks,
    + .num_clks = ARRAY_SIZE(vdec_soc_clks),
    +};
    +
    +static const struct of_device_id of_match_clk_mt8192_vdec[] = {
    + {
    + .compatible = "mediatek,mt8192-vdecsys",
    + .data = &vdec_desc,
    + }, {
    + .compatible = "mediatek,mt8192-vdecsys_soc",
    + .data = &vdec_soc_desc,
    + }, {
    + /* sentinel */
    + }
    +};
    +
    +static struct platform_driver clk_mt8192_vdec_drv = {
    + .probe = mtk_clk_simple_probe,
    + .driver = {
    + .name = "clk-mt8192-vdec",
    + .of_match_table = of_match_clk_mt8192_vdec,
    + },
    +};
    +
    +builtin_platform_driver(clk_mt8192_vdec_drv);
    --
    2.18.0
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