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    Subject[v14 16/21] clk: mediatek: Add MT8192 mfgcfg clock support
    Date
    Add MT8192 mfgcfg clock provider

    Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
    Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    ---
    drivers/clk/mediatek/Kconfig | 6 ++++
    drivers/clk/mediatek/Makefile | 1 +
    drivers/clk/mediatek/clk-mt8192-mfg.c | 50 +++++++++++++++++++++++++++
    3 files changed, 57 insertions(+)
    create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c

    diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
    index 59104b8cd7dc..e212f3416855 100644
    --- a/drivers/clk/mediatek/Kconfig
    +++ b/drivers/clk/mediatek/Kconfig
    @@ -544,6 +544,12 @@ config COMMON_CLK_MT8192_MDPSYS
    help
    This driver supports MediaTek MT8192 mdpsys clocks.

    +config COMMON_CLK_MT8192_MFGCFG
    + bool "Clock driver for MediaTek MT8192 mfgcfg"
    + depends on COMMON_CLK_MT8192
    + help
    + This driver supports MediaTek MT8192 mfgcfg clocks.
    +
    config COMMON_CLK_MT8516
    bool "Clock driver for MediaTek MT8516"
    depends on ARCH_MEDIATEK || COMPILE_TEST
    diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
    index 7b258cb1f914..024841a79f1c 100644
    --- a/drivers/clk/mediatek/Makefile
    +++ b/drivers/clk/mediatek/Makefile
    @@ -74,5 +74,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o
    obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP) += clk-mt8192-imp_iic_wrap.o
    obj-$(CONFIG_COMMON_CLK_MT8192_IPESYS) += clk-mt8192-ipe.o
    obj-$(CONFIG_COMMON_CLK_MT8192_MDPSYS) += clk-mt8192-mdp.o
    +obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o
    obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
    obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
    diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c
    new file mode 100644
    index 000000000000..3bbc7469f0e4
    --- /dev/null
    +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c
    @@ -0,0 +1,50 @@
    +// SPDX-License-Identifier: GPL-2.0-only
    +//
    +// Copyright (c) 2021 MediaTek Inc.
    +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    +
    +#include <linux/clk-provider.h>
    +#include <linux/of_device.h>
    +#include <linux/platform_device.h>
    +
    +#include "clk-mtk.h"
    +#include "clk-gate.h"
    +
    +#include <dt-bindings/clock/mt8192-clk.h>
    +
    +static const struct mtk_gate_regs mfg_cg_regs = {
    + .set_ofs = 0x4,
    + .clr_ofs = 0x8,
    + .sta_ofs = 0x0,
    +};
    +
    +#define GATE_MFG(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
    +
    +static const struct mtk_gate mfg_clks[] = {
    + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0),
    +};
    +
    +static const struct mtk_clk_desc mfg_desc = {
    + .clks = mfg_clks,
    + .num_clks = ARRAY_SIZE(mfg_clks),
    +};
    +
    +static const struct of_device_id of_match_clk_mt8192_mfg[] = {
    + {
    + .compatible = "mediatek,mt8192-mfgcfg",
    + .data = &mfg_desc,
    + }, {
    + /* sentinel */
    + }
    +};
    +
    +static struct platform_driver clk_mt8192_mfg_drv = {
    + .probe = mtk_clk_simple_probe,
    + .driver = {
    + .name = "clk-mt8192-mfg",
    + .of_match_table = of_match_clk_mt8192_mfg,
    + },
    +};
    +
    +builtin_platform_driver(clk_mt8192_mfg_drv);
    --
    2.18.0
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