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    Subject[RFC 0/5] Support non-coherent DMA on RISC-V using a global pool
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    RISC-V privilege specification doesn't define an IOMMU or any method modify
    PMA attributes or PTE entries to allow non-coherent mappings yet. In
    the beginning, this approach was adopted assuming that most of the RISC-V
    platforms would support full cache-coherent IO. Here is excerpt from the
    priv spec section 3.6.5

    "In RISC-V platforms, the use of hardware-incoherent regions is discouraged
    due to software complexity, performance, and energy impacts."

    While some of the RISC-V platforms adhere to the above suggestion, not all
    platforms can afford to build to fully cache-coherent I/O devices. To
    address DMA for non-coherent I/O devices, we need to mark a region of memory
    as non-cacheable. Some of the platforms rely on a fixed region of uncached
    memory that is remapped to the system memory while some other modify
    the PTE entries to achieve that.

    The patch3 solves the issue for the fist use case by using a global
    pool of memory that is reserved for DMA. The device access the reserved area
    of the region while corresponding CPU address will be from uncached region
    As the uncached region is remapped to the beginning of the system ram, both
    CPU and device get the same view.

    To facilitate streaming DMA APIs, patch 1 introduces a set of generic
    cache operations. Any platform can use the generic ops to provide platform
    specific cache management operations. Once the standard RISC-V CMO extension
    is available, it will also use these generic ops.

    To address the second use case, Page Based Memory Attribute (PBMT) extension
    is proposed. Once the extension is in good shape, we can leverage that
    using CONFIG_DIRECT_REMAP. Currently, it is selected via a compile time config
    option. We will probably need another arch specific hooks to know if the
    platform supports direct remap at runtime. For RISC-V, it will check the
    presence of PBMT extension while other arch function will simply return true
    if DIRECT_REMAP is enabled. This is required as arious different config
    (DIRECT_REMAP, GLOBAL_POOL) will be enabled in the defconfig so that a
    unified kernel image can boot on all RISC-V platforms.

    This patch series depends on Christoph's global pool support series[1].
    Tested on Qemu, HiFive unleashed and beagleV. This series is also available
    at [2].
    This series also solves the non-coherent DMA support on beagleV but requires
    additional beagleV specific patches[3] which will be upstreamed soon.


    [1] https://lists.linuxfoundation.org/pipermail/iommu/2021-July/057266.html
    [2] https://github.com/atishp04/linux/tree/riscv_nc_global_pool
    [3] https://github.com/atishp04/linux/tree/wip_beaglev_dma_nc_global

    Atish Patra (5):
    RISC-V: Implement arch_sync_dma* functions
    of: Move of_dma_get_range to of_address.h
    dma-mapping: Enable global non-coherent pool support for RISC-V
    dma-direct: Allocate dma pages directly if global pool allocation
    fails
    RISC-V: Support a new config option for non-coherent DMA

    arch/riscv/Kconfig | 8 +++
    arch/riscv/include/asm/dma-noncoherent.h | 19 +++++++
    arch/riscv/mm/Makefile | 1 +
    arch/riscv/mm/dma-noncoherent.c | 66 ++++++++++++++++++++++++
    drivers/of/of_private.h | 10 ----
    include/linux/of_address.h | 12 +++++
    kernel/dma/coherent.c | 49 +++++++++++++++---
    kernel/dma/direct.c | 7 ++-
    8 files changed, 152 insertions(+), 20 deletions(-)
    create mode 100644 arch/riscv/include/asm/dma-noncoherent.h
    create mode 100644 arch/riscv/mm/dma-noncoherent.c

    --
    2.31.1

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