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    Subject[PATCH 5.13 077/156] arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
    Date
    From: Punit Agrawal <punitagrawal@gmail.com>

    [ Upstream commit 8efe01b4386ab38a36b99cfdc1dc02c38a8898c3 ]

    The PCIe host bridge on RK3399 advertises a single 64-bit memory
    address range even though it lies entirely below 4GB.

    Previously the OF PCI range parser treated 64-bit ranges more
    leniently (i.e., as 32-bit), but since commit 9d57e61bf723 ("of/pci:
    Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses")
    the code takes a stricter view and treats the ranges as advertised in
    the device tree (i.e, as 64-bit).

    The change in behaviour causes failure when allocating bus addresses
    to devices connected behind a PCI-to-PCI bridge that require
    non-prefetchable memory ranges. The allocation failure was observed
    for certain Samsung NVMe drives connected to RockPro64 boards.

    Update the host bridge window attributes to treat it as 32-bit address
    memory. This fixes the allocation failure observed since commit
    9d57e61bf723.

    Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
    Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
    Suggested-by: Robin Murphy <robin.murphy@arm.com>
    Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
    Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
    Link: https://lore.kernel.org/r/20210607112856.3499682-5-punitagrawal@gmail.com
    Signed-off-by: Heiko Stuebner <heiko@sntech.de>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
    index 1703817c7354..7f8081f9e30e 100644
    --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
    +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
    @@ -227,7 +227,7 @@
    <&pcie_phy 2>, <&pcie_phy 3>;
    phy-names = "pcie-phy-0", "pcie-phy-1",
    "pcie-phy-2", "pcie-phy-3";
    - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
    + ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
    <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
    resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
    <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
    --
    2.30.2


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