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    Subject[PATCH 5.13 081/156] arm64: dts: imx8: conn: fix enet clock setting
    Date
    From: Dong Aisheng <aisheng.dong@nxp.com>

    [ Upstream commit dfda1fd16aa71c839e4002109b0cd15f61105ebb ]

    enet_clk_ref actually is sourced from internal gpr clocks
    which needs a default rate. Also update enet lpcg clock
    output names to be more straightforward.

    Cc: Abel Vesa <abel.vesa@nxp.com>
    Cc: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    .../boot/dts/freescale/imx8-ss-conn.dtsi | 50 ++++++++++++-------
    1 file changed, 32 insertions(+), 18 deletions(-)

    diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
    index e1e81ca0ca69..a79f42a9618e 100644
    --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
    +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
    @@ -77,9 +77,12 @@ conn_subsys: bus@5b000000 {
    <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
    <&enet0_lpcg IMX_LPCG_CLK_2>,
    - <&enet0_lpcg IMX_LPCG_CLK_1>,
    + <&enet0_lpcg IMX_LPCG_CLK_3>,
    <&enet0_lpcg IMX_LPCG_CLK_0>;
    clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
    + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
    + <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
    + assigned-clock-rates = <250000000>, <125000000>;
    fsl,num-tx-queues=<3>;
    fsl,num-rx-queues=<3>;
    power-domains = <&pd IMX_SC_R_ENET_0>;
    @@ -94,9 +97,12 @@ conn_subsys: bus@5b000000 {
    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
    <&enet1_lpcg IMX_LPCG_CLK_2>,
    - <&enet1_lpcg IMX_LPCG_CLK_1>,
    + <&enet1_lpcg IMX_LPCG_CLK_3>,
    <&enet1_lpcg IMX_LPCG_CLK_0>;
    clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
    + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
    + <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
    + assigned-clock-rates = <250000000>, <125000000>;
    fsl,num-tx-queues=<3>;
    fsl,num-rx-queues=<3>;
    power-domains = <&pd IMX_SC_R_ENET_1>;
    @@ -152,15 +158,19 @@ conn_subsys: bus@5b000000 {
    #clock-cells = <1>;
    clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
    <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
    - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
    + <&conn_axi_clk>,
    + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
    + <&conn_ipg_clk>,
    + <&conn_ipg_clk>;
    clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    - <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
    - <IMX_LPCG_CLK_5>;
    - clock-output-names = "enet0_ipg_root_clk",
    - "enet0_tx_clk",
    - "enet0_ahb_clk",
    - "enet0_ipg_clk",
    - "enet0_ipg_s_clk";
    + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
    + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
    + clock-output-names = "enet0_lpcg_timer_clk",
    + "enet0_lpcg_txc_sampling_clk",
    + "enet0_lpcg_ahb_clk",
    + "enet0_lpcg_rgmii_txc_clk",
    + "enet0_lpcg_ipg_clk",
    + "enet0_lpcg_ipg_s_clk";
    power-domains = <&pd IMX_SC_R_ENET_0>;
    };

    @@ -170,15 +180,19 @@ conn_subsys: bus@5b000000 {
    #clock-cells = <1>;
    clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
    <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
    - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
    + <&conn_axi_clk>,
    + <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
    + <&conn_ipg_clk>,
    + <&conn_ipg_clk>;
    clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    - <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
    - <IMX_LPCG_CLK_5>;
    - clock-output-names = "enet1_ipg_root_clk",
    - "enet1_tx_clk",
    - "enet1_ahb_clk",
    - "enet1_ipg_clk",
    - "enet1_ipg_s_clk";
    + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
    + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
    + clock-output-names = "enet1_lpcg_timer_clk",
    + "enet1_lpcg_txc_sampling_clk",
    + "enet1_lpcg_ahb_clk",
    + "enet1_lpcg_rgmii_txc_clk",
    + "enet1_lpcg_ipg_clk",
    + "enet1_lpcg_ipg_s_clk";
    power-domains = <&pd IMX_SC_R_ENET_1>;
    };
    };
    --
    2.30.2


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